AM2434: Maximum clock frequency for OSPI Flash

Hi Daisuke,

To answer your questions, I'll lay down some facts about the OSPI controller:



1. If the PHY is not enabled, maximum output clock speed the OSPI controller can safely operate at is 50MHz. How you achieve this using the input clock and divider is upto you. It is recommended to keep the divider value as multiples of 4 for stability. So one recommended way to achieve this is 200 MHz input clock and divider as 4. You can set these in the SysConfig of the example.

2. If the PHY is disabled, the divider value is ignored. So output clock = input clock.

3. It is recommended to use the PHY mode only using reads. In all the other times, it is best to restrain from using the PHY because there is no real value. Other than read, the only operations are write and erase. Their performance is not entirely dependent on the data we sent. Time taken for both erase and write operations highly depend on the flash. After writing each page (generally 256 bytes), the OSPI controller will have to wait for a flash-specific time period till it can write the next page. So even if you could enable the PHY during writes in theory, the stall time after every page write is not going to reduce. If we take the case of erase, there is not much data going from OSPI to the flash anyway. The time taken to erase a particular sector/block is again dependent on the flash.

On top of this, for STIG operations or for sending commands to the flash other than read, write or erase, PHY is not recommended. So it was a design choice to use the PHY only for reads. But PHY with writes is tested (at least experimentally). So you could in theory enable PHY during a page write and disable it write after that.

If there is a need to have PHY enabled for operations other than read, there are ways to do it like I mentioned above. But without PHY, the maximum safe speed is 50 MHz. So setting the divider value to 1 or 2 which would result in output clock > 50 MHz would not be a good idea.


So to help you better, let me know what exact usecase the customer is looking for here.

Regards,
Anand M

Daisuke-san,

Apologies. My mistake. It was a typo. You're right. If the PHY is enabled, then the divider value is ignored. So output clock = input clock in that case. And yes, the customer can go forward with DQS clocking. Let me know if you have any more queries.

Regards,
Anand M