AM2634-Q1: SemaphoreP in epwm example

Sung-IL

Mastermind 30190 points

Part Number: AM2634-Q1

Dear Champs,

I found there were SemaphoreP APIs in epwm example.

for example, in epwm_hr_duty_cycle.c example, I found below SemaphoreP APIs as below.

Could you please let me know why these SemaphoreP APIs used in these epwm examples?

Should these SemaphoreP APIs be used in single core application?

Should these SemaphoreP APIs be used in multi-core application even when only one core access epwm?

Where I can find details on these Semaphore APIs?

Actually when my customer implemented their own source to use epwm ISR without these Semaphore APIs, they faced hang in the ISR. Should they add these Semaphore APIs?

~~~~~~`

/* Get Address of ePWM */
gEpwmBaseAddr = CONFIG_EPWM_BASE_ADDR;

status = SemaphoreP_constructCounting(&gEpwmSyncSemObject, 0, numIsrCnt);
DebugP_assert(SystemP_SUCCESS == status);

/* Register & enable interrupt */
HwiP_Params_init(&hwiPrms);
/* Integrate with Syscfg */
hwiPrms.intNum = CSLR_R5FSS0_CORE0_CONTROLSS_INTRXBAR0_OUT_0;
hwiPrms.callback = &App_epwmIntrISR;
/* Integrate with Syscfg */
hwiPrms.isPulse = APP_INT_IS_PULSE;
status = HwiP_construct(&gEpwmHwiObject, &hwiPrms);
DebugP_assert(status == SystemP_SUCCESS);

EPWM_clearEventTriggerInterruptFlag(gEpwmBaseAddr);

while(numIsrCnt > 0)
{
SemaphoreP_pend(&gEpwmSyncSemObject, SystemP_WAIT_FOREVER);
numIsrCnt--;
}

EPWM_disableInterrupt(gEpwmBaseAddr);
EPWM_clearEventTriggerInterruptFlag(gEpwmBaseAddr); /* Clear any pending interrupts if any */
HwiP_destruct(&gEpwmHwiObject);
SemaphoreP_destruct(&gEpwmSyncSemObject);

DebugP_log("EPWM Duty Cycle Test Passed!!\r\n");
DebugP_log("All tests have passed!!\r\n");

Board_driversClose();
Drivers_close();
}

~~~~~~~

Thanks and Best Regards,

SI.

over 2 years ago

+1 Sri Vidya Gunturi over 2 years ago

TI__Expert 7585 points

The epwm duty cycle example flow is explained below:

1. epwm is configured for period, compare registers, etc.

2. epwm interrupt is configured, for the counter = 0 event --> through Syscfg

3. This configured interrupt is registered for the ISR function callback --> App_epwmIntrISR

4. In the While loop, Semaphore Pend is given. Hence the code waits here until the semaphore is unlocked/serviced.

5. When the EPWM interrupt is triggered, the semaphore is unlocked here (SemaphoreP_post(&gEpwmSyncSemObject);) signifying that interrupt has occured.

6. Now the code passes through the semaphore wait in the while loop and decrements the numIsrCnt integer.

7. This continues till numIsrCnt reaches 0.

8. Then the code exits and PWMs are reset.

Sung-IL said:
Could you please let me know why these SemaphoreP APIs used in these epwm examples?

Here sempahores are used to demonstrate the ISR trigger and flow, Its not mandatory to use the Semaphore APIs.

Sung-IL said:
Should these SemaphoreP APIs be used in single core application?

Should these SemaphoreP APIs be used in multi-core application even when only one core access epwm?

These are for single core application.

Sung-IL said:
Where I can find details on these Semaphore APIs?

Please find more detailed explanation here:

https://software-dl.ti.com/mcu-plus-sdk/esd/AM263X/latest/exports/docs/api_guide_am263x/group__KERNEL__DPL__SEMAPHORE.html#ga2de8d925b9ae035fd8a749927463aef5

https://software-dl.ti.com/mcu-plus-sdk/esd/AM263X/latest/exports/docs/api_guide_am263x/KERNEL_DPL_SEMAPHORE_PAGE.html

Sung-IL said:
Actually when my customer implemented their own source to use epwm ISR without these Semaphore APIs, they faced hang in the ISR. Should they add these Semaphore APIs?

Semaphore APIs are not mandatory.

Make the while loop as below:

while(1)

{

}

So that there wont be any counter decrementing and no semaphore pend.

static void App_epwmIntrISR(void *handle)
{
volatile bool status;

status = EPWM_getEventTriggerInterruptStatus(gEpwmBaseAddr);
if(status == true)
{
EPWM_clearEventTriggerInterruptFlag(gEpwmBaseAddr);
}

return;
}

This should provide required PWM waveforms. (instance in the example is EPWM9)

Thanks & Regards

Sri Vidya

0 Sung-IL over 2 years ago in reply to Sri Vidya Gunturi

TI__Mastermind 30190 points

Thanks for the immediate response.

What is the meaning of 'APP_INT_IS_PULSE (1U)' in epwm_hr_duty_cycle example?

Thanks and Best Regards,

SI.

+1 Sri Vidya Gunturi over 2 years ago in reply to Sung-IL

TI__Expert 7585 points

Sure, no problem!

Sung-IL said:
meaning of 'APP_INT_IS_PULSE (1U)'

Its for configuring the interrupt in pulse mode.

/**

* \brief Parameters passed during \ref HwiP_construct

typedef struct HwiP_Params_ {

uint32_t intNum; /**< CPU interrupt number. */

HwiP_FxnCallback callback; /**< Callback to call when interrupt is received */

void *args; /**< Arguments to pass to the callback */

uint16_t eventId; /**< Event ID to register against, only used with c6x with event combiner */

uint8_t priority; /**< Interrupt priority, only used with ARM R5, ARM M4 */

uint8_t isFIQ; /**< 0: Map interrupt as ISR, 1: map interrupt as FIQ, only used with ARM R5 */

uint8_t isPulse; /**< 0: Map interrupt as level interrupt, 1: Map interrupt as pulse interrupt, only used with ARM R5, ARM M4 */

} HwiP_Params;

software-dl.ti.com/.../structHwiP__Params.html

Regards

Sri Vidya

0 Sung-IL over 2 years ago in reply to Sri Vidya Gunturi

TI__Mastermind 30190 points

Hi Sri Vidya,

My customer found it was not returned from ISR routine and the function in the main function was not called.

e.g. it looks like new ISRs were occurred before returning from previous ISR.

When they added breakpoints in ISR and main function, it was not stopped in main function breakpoint. only stopped at the breakpoint in ISR.

When I tried to step over each instruction in ISR, there is no issue to return to main function.

May I ask your opinion on my customer's issue?

I tried to increase IRQ stack size, but it was not help to resolve this issue.

One thing my customer found is ISR code is in uncached region and it takes much time to return.

When they set the pwm counter to 1000, they found it take 200 TBCTR to return.

Do you think this could be an issue and they can resolve it when they allocate ISR in TCM memory?

Thanks and Best Regards,

SI.

0 Sri Vidya Gunturi over 2 years ago in reply to Sung-IL

TI__Expert 7585 points

Sung-IL said:
My customer found it was not returned from ISR routine and the function in the main function was not called.

Is it the customer code? what changes are made? Is it possible to share the code?

The example function was tested and it works, I can confirm that.

Sung-IL said:
One thing my customer found is ISR code is in uncached region and it takes much time to return.

When they set the pwm counter to 1000, they found it take 200 TBCTR to return.

Could you also try the same in release mode? the release mode reduces Software overhead. Yes placing the ISR in TCM should help reduce the time.

The ISR Latency is around 400 to 800n sec. This is the time taken to service the ISR and return from the ISR to main function. This is caused for switching from the main to ISR, context saving and stacking and then unstacking and returning from ISR to main function.

Thanks & Regards

Sri Vidya