TMS570LS1115: Possible causes of chip failure

Hi Cherry,

Cherry Zhou said:

the master chip is not working when there is no communication.

Is tms570ls1115 the master? When failure occurs, what is the value of ESM group 3 state register?

The startup code checks if there were ESM group3 errors during power-up. These error could occur during eFuse auto-load or during reads from flash OTP during power-up. Device operation is not reliable and not recommended in this case. An ESM group3 error only drives the nERROR pin low. An external circuit that monitors the nERROR pin must take the appropriate action to ensure that the system is placed in a safe state, as determined by the application.

How does your code handle the ESM group 3 errors during the startup?

Cherry Zhou said:

could you please help provide several possible causes of the 579 chip failure?

What does "579 chip failure" mean?

Hi QJ Wang

Troubleshoot sporadic non-communication problems. The main control chip is stuck in the PLL-related while loop.

Please refer the fiels about test.

TI fiels show that there would be few PLL fails to start about 570,Could you please help provide the PPM about this phenomenon？JEE Test Report.pptx

1055.JEE Test Report.pptx

Do you mean the code got stuck in this while loop?

while ((SYS_CSVSTAT & ((SYS_CSDIS ^ 0xFFU) & 0xFFU)) != ((SYS_CSDIS ^ 0xFFU) & 0xFFU))
{
       SYS_CSVSTAT = systemREG1->CSVSTAT;
       SYS_CSDIS = systemREG1->CSDIS;
} /* Wait */

What is the value of those two registers: CSVSTAT and CSDIS?

CSVSTAT：0xBB；CSDIS：0x8C

TI fiels show that there would be few PLL fails to start about 570,Could you please help provide the PPM about this phenomenon？

Any Update about this case?

The CSVSTAT should be 0xFB. The 6th clock source is PLL2 which is implemented in TMS570LS1115 device. 

Is PLL2 disabled by your code?

Maybe it is, how can i confirm it? Is this phenomenon the same as the errata？

TI fiels show that there would be few PLL fails to start about 570,Could you please help provide the PPM about this phenomenon？

Hi,

The PLL (PLL1 and PLL2) is disabled by default on power-up, the CSVSTAT is 0xB9. The PLL should be enabled after programming PLLCTL1/2/3.

After PLL1 and PLL2 are enabled, the CSVSTAT becomes 0xFB. 

If PLL2 is not enabled in your code, the CSVSTAT is 0xBB. 

Please check the code in setupPLL():

/** - Enable PLL(s) to start up or Lock */
systemREG1->CSDIS = 0x00000000U
| 0x00000000U
| 0x00000008U
| 0x00000080U
| 0x00000000U
| 0x00000000U
| 0x00000000U;

If the PLL1 and PLL2 are enabled, but the PLL2 bit of CSVSTAT is set  --> errata SYS#46. I don't know the PPM

is thar right?

Yes, it is correct.