RM57L843: Inconsistencies in RM57Lx TRM

Hi Christian,

Christian Bauer said:

SPI Module: Table 27-25 for the explanation of the CSNR field of the SPIDAT1 register suggests that a '1' bit activates the corresponding chip select line, but it actually seems to be inverted. That is, to activate CS0, for example, you have to set the value 3Eh, not 01h as indicated in the table. Is this correct?

Actually, the chip selects can be used as either active low or active high, please have a look on below highlighted sentence.

It is so simple to act CS as active high, we can just need to configure default sate as logic-0 using SPIDEF register

That is the reason they mentioned "X" in the table, which means don't care.

So, the values are correct in the w.r.t active high signals.

Christian Bauer said:

System Control Registers: Section 2.5.1.46 describes bit 6 of the SYSESR register as "Reserved", while the TI code treats it like a second CPU reset flag. Which is correct?

Can you please point out where exactly in the code, treating as second CPU reset flag. Either screenshot or code snippet is good for easy understanding.

Christian Bauer said:

PBIST Module: Section 9.5.2 describes bit 3 of the DLR register as "Reserved", with the warning "Do not change this bit from its default value of 1". Yet the programming example in section 9.6.1 says to set "DLR = 0x14" which would clear this bit. Which is correct?

You are right about this Christian, i will discuss with my internal team on this. Thanks for pointing this out.

Christian Bauer said:

PBIST Module: Section 9.5.3 only defines bit 0 of the PACT register and the example in section 9.6.1 says to write "PACT = 0x1", but the TI code and the flow diagram in Figure 9-2 write "PACT = 0x03" which also sets bit 1. What is the function of bit 1 and what is the correct value to write to PACT?

You are right about this Christian, i will discuss with my internal team on this. Thanks for pointing this out.

--

Thanks & regards,
Jagadish.

Regarding the reset flags: Both HALCoGen (older version) and SafeTI library have definitions like this:

include/HL_system.h:

typedef enum
{
...
  INTERCONNECT_RESET = 0x0080U, /**< Alias for Interconnect Reset */
  CPU1_RESET = 0x0040U, /**< Alias for CPU 1 Reset */
  CPU0_RESET = 0x0020U, /**< Alias for CPU 0 Reset */
...
}resetSource_t;

hal/include/reg_bitdefn_system.h:

#if defined(_TMS570LC43x_) || defined(_RM57Lx_)
#define SYSESR_CPURST0 (uint32)0x00000020u
#define SYSESR_CPURST1 (uint32)0x00000040u
#define SYSESR_ICSTRST (uint32)0x00000080u
#endif

And check both flags when determining the reset reason:

source/HL_system.c:

else if ((SYS_EXCEPTION & (uint32)CPU1_RESET) !=0U)
{
  /* Reset caused due to CPU1 reset.
     CPU reset can be caused by CPU self-test completion, or
     by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
  rst_source = CPU1_RESET;
  SYS_EXCEPTION = (uint32)CPU1_RESET;
}
else if ((SYS_EXCEPTION & (uint32)CPU0_RESET) !=0U)
{
  /* Reset caused due to CPU0 reset.
     CPU reset can be caused by CPU self-test completion, or
     by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
  rst_source = CPU0_RESET;
  SYS_EXCEPTION = (uint32)CPU0_RESET;
}

safety_library/source/sl_init.c:

#if defined(_TMS570LC43x_) || defined(_RM57Lx_)
else if (SYSESR_CPURST1 == (sysEsr & SYSESR_CPURST1)) {
  /*
   * This reset is generated by the CPU self-test controller (LBIST) or by changing
   * the memory protection (MMU/MPU) configuration in the CPURSTCR register. This
   * reset is flagged by the CPU RST bit of the SYSESR register, SYSESR[5].
   */
  retVal = RESET_TYPE_CPU1;
  /*SAFETYMCUSW 440 S MR: 11.3 <APPROVED> Comment_5*/
  sl_systemREG1->SYSESR = SYSESR_CPURST1;
}
else if (SYSESR_CPURST0 == (sysEsr & SYSESR_CPURST0)) {
  /*
   * This reset is generated by the CPU self-test controller (LBIST) or by changing
   * the memory protection (MMU/MPU) configuration in the CPURSTCR register. This
   * reset is flagged by the CPU RST bit of the SYSESR register, SYSESR[5].
   */
  retVal = RESET_TYPE_CPU0;
  /*SAFETYMCUSW 440 S MR: 11.3 <APPROVED> Comment_5*/
  sl_systemREG1->SYSESR = SYSESR_CPURST0;
}
#endif

Since the SafeTI library in particular puts this in a defined(_RM57Lx_) section, I figured that this register bit must have a function.

Regards,
Christian

Christian Bauer said:

Regarding the reset flags: Both HALCoGen (older version) and SafeTI library have definitions like this:

Thanks for sharing this info Christian, I understood the issue now and i will discuss with my team on this.

--

Thanks & regards,

Jagadish.