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LP-AM243: AM2434 QSPI Flash Question

AndreTseng
Intellectual 2505 points
Part Number: LP-AM243
Other Parts Discussed in Thread: SYSCONFIG

Hi,

       In the AM243-LP schematic, OSPI0_CSN1(M20) is configured to GPIO0_12 (GPIO_OSPI0_RESET_N).

 

The GPIO0_12 connect to AND gate to control QSPI_RST_N, but we can’t find this GPIO setting in sysconfig of firmware project.

 

  1. Which scenario may use this GPIO to control QSPI Reset?
  2. Can we move this GPIO feature to other pin?

 

Regards

Andre

  • 0
    TI__Intellectual 2505 points

    Team,

        Any update? 

    Regards

    Andre

  • 0 in reply to AndreTseng
    TI__Expert 5770 points

    Hi Andre,

    AndreTseng said:
    Which scenario may use this GPIO to control QSPI Reset?

    the signal is pulled high by default. Like you mentioned, this signal is connected to an AND gate in the following way in our LP:

    From the above, you can conclude that the QSPI_RST_N signal will be low when either of the two inputs (GPIO_OSPI0_RESET_N and MCU_RESETSTATz) go low, asserting the RESET# on the flash. The GPIO is just a way of providing software control for the reset signal going to the flash, since at any point you can set it low in software to assert the reset.

    AndreTseng said:
    Can we move this GPIO feature to other pin?

    Yes, any GPIO can serve the same purpose if you set them as a high output. 

    Best,

    Daniel