RM57L843: Fault injection can not trigger ESM interrupt by using API SL_SelfTest_SRAM

shenruming

Part Number: RM57L843

Hi,

1. The ESM interrupt "ESM_G1ERR_L2RAMW_CORRERR" was not triggered after we use "SL_SelfTest_SRAM" with passing test type "SRAM_ECC_ERROR_FORCING_1BIT" to insert L2RAMW SECDED 1-Bit ECC error.

2. The ESM interrupt "ESM_G2ERR_L2RAMW_UNCORR_B" was not triggered after we use "SL_SelfTest_SRAM" with passing test type "SRAM_ECC_ERROR_FORCING_2BIT" to insert L2RAMW SECDED 2-Bit ECC error.

By debugging with CCS, I found that the program suspends at below place during the fault injection test of SRAM ECC 1bit:

And the program suspends at below place during the fault injection test of SRAM ECC 2bit:

Can you help please check if anything wrong in your diagnostic library code as below?

Have you tested all the APIs and verified their usability on RM57L843? If yes, can you help provide the test report for our reference. Thanks so much.

5342.sl_selftest.c

over 1 year ago

0 QJ Wang over 1 year ago

TI__Guru**** 192956 points

I am testing the APIs of SRAM self-test.

0 QJ Wang over 1 year ago

TI__Guru**** 192956 points

shenruming said:
1. The ESM interrupt "ESM_G1ERR_L2RAMW_CORRERR" was not triggered after we use "SL_SelfTest_SRAM" with passing test type "SRAM_ECC_ERROR_FORCING_1BIT" to insert L2RAMW SECDED 1-Bit ECC error.

There is no problem to get ESM 2.7 set and ESM interrupt (IntOffstHgh = 0x28 --> ESM 2.7)

0 shenruming over 1 year ago in reply to QJ Wang

Intellectual 575 points

Hi QJ,

Can you give ideas on the debugging steps? which registers should be examined?

0 QJ Wang over 1 year ago in reply to shenruming

TI__Guru**** 192956 points

There are several "gates" before an interrupt request gets to the CPU:

1. The module that generates an interrupt request has a register to enable each interrupt that it can generate.

ESMIESR1/4/7 registers

2. The Vectored Interrupt Manager (VIM) has registers to allow an interrupt request from a module to be forwarded to the CPU as per the priority scheme (lower channel number first).

VIM channel 20 for ESM low level interrupt,

VIM channel 0 is for ESM high-level interrupt (NMI)

3. Finally the CPU itself must be configured to respond to the interrupt requests forwarded by the VIM (IRQ or FIQ).

Bit I and F of MCU CPSR register

0 shenruming over 1 year ago in reply to QJ Wang

Intellectual 575 points

Hi QJ,

Thanks for your detailed clarification.

The current problem is: the program will stop running when it reaches line "sl_l2ramwREG->DIAG_ECC = (*eccB1) ^ L2RAM_SYN_2BIT_DATA_ECC"

or "sl_l2ramwREG->DIAG_ECC = (*eccB1) ^ L2RAM_SYN_1BIT_DATA_ECC", and no ESM fault interrupt at this time.

What factors could cause this situation?

0 QJ Wang over 1 year ago in reply to shenruming

TI__Guru**** 192956 points

Hi Shenruming,

Never got this kind of issue. Do you mean that the code gets stuck at this statement (sl_l2ramwREG->DIAG_ECC = (*eccB1) ^ L2RAM_SYN_2BIT_DATA_ECC)? Did you get data abort or prefetch abort? When the code gets stuck or hang at this statement, what is the value of ESM status registers?

Can the power-cycle resolve the hang-up issue?

0 shenruming over 1 year ago in reply to QJ Wang

Intellectual 575 points

Hi QJ,

Yes, the code gets stuck at the statement "sl_l2ramwREG->DIAG_ECC = (*eccB1) ^ L2RAM_SYN_2BIT_DATA_ECC)".

Specifically, during the single step debug, the program jumps to below position after running "sl_l2ramwREG->DIAG_ECC = (*eccB1) ^ L2RAM_SYN_2BIT_DATA_ECC)", and then stops executing the next statement.