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AM2634-Q1: Power up sequence: possible impact of 1V2 Core supply being up after 3V3 and PORz

Nilton Spagnol Trento
Prodigy 51 points
Part Number: AM2634-Q1
Other Parts Discussed in Thread: AM2634

Hello,

we are using a PMIC to supply all necessary voltages to the AM2634 in our prototype. The PMIC has a pre-regulator of 5V8 and the 3V3 as post-regulator supplies the VDDS33 for Sitara, but the 1V2 core voltage of Sitara is generated by an extern post-regulator that is turning on after the 3V3. So, the PORz is on when the 3V3 is on, so 3V3 and PORz are up before the 1V2 core voltage. According to the documentation, the device should be held in reset until all power supplies are stable with an additional a delay for the High Frequency Oscillator (HFOSC0) clock to stabilize.

 This is being tracked in our design errata sheet and it will be solved for the production. What is the impact of having the 3V3 and PORz up before the 1V2 core voltage?

Is it okay for the 3V3 and PORz being up before the 1V2 as long as the HFOSC0 (XTAL_IN) is stable after 1V2?

The prototype is working so far, but we had a few boards with strange faults that we could not find the root cause. One of them was a short in the 3V3 pins of Sitara. 

Below an scope measurement of the initialization sequence.

CH1 blue is PMIC 5V8 pre-regulator, CH2 magenta is PORz, CH3 yellow is 1V2, CH4 green is XTAL_IN signal.

  • +1
    TI__Mastermind 18220 points

    Hi Nilton, 

    Nilton Spagnol Trento said:
     This is being tracked in our design errata sheet and it will be solved for the production. What is the impact of having the 3V3 and PORz up before the 1V2 core voltage?

    As you have stated, as shown in the datasheet, Figure 7-1 the AM263x device is required to be held in reset until 1.2V and 3.3V power is valid. Reset behavior and subsequent functionality cannot be guaranteed without this power valid state being present prior to PORZ being toggled high. We have not verified every combination of power and on reset sequence so we do not know exactly what may or may not reset correctly when the device is subjected to unsupported reset sequences. 

    Nilton Spagnol Trento said:
    Is it okay for the 3V3 and PORz being up before the 1V2 as long as the HFOSC0 (XTAL_IN) is stable after 1V2?

    No. This is an undefined state. The oscillator is only one item that may/may not come out of reset correctly or perform incorrectly when an unsupported reset sequence is applied.

    I can only recommend that you modify/revise the design to follow the datasheet reset sequence. 

    Thank you,

    -Randy

  • 0 in reply to Randy Rosales
    Prodigy 51 points

    Hi Randy,

    Thank you for your fast response. 

    I would like to give the feedback that the way this information was documented in this part of the datasheet was confusing, because the datasheet pg. 77 says that there is no sequencing requirement with respect to the primary core digital 1V2 and IO power 3V3 for the AM263x device. Here it should be informed clearly that the sequencing of both 3V3 and 1V2 needs to be stable so that the PORz can be released. Yes, I agree the figure 7-1 shows that, but only in the TRM pg. 199 we found that both 3V3 and 1V2 needs to be within range before releasing the PORz. 

    Thanks and regards,

    - Nilton