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SM470R1B1M-HT: SCI3+DMA data reception exception - byte misalignment

Part Number: SM470R1B1M-HT

Hi,

SM470 communicates serially with external devices through SCI3 and is controlled by DMA. Two DMA packages (package0, package1) are configured in the program. Package0 (controlling SCI3 TX) is used to send data return commands to external devices, and package1 (controlling SCI3 RX) is used to automatically receive response data from external devices (total data length 4 bytes). After starting DMA, package0 works first to complete the sending of the data return command; package1 works later to wait for the response data from the external device. The above interactive process is executed 128 times per second, and works normally in most cases, but sometimes the following exceptions occur:

0. System reset;

1. Start the first data interaction with the external device: the external device returns 4 bytes of data normally; the DMA should trigger the DMA reception completion interrupt after the external device responds with 4 bytes. In fact, the reception completion interrupt is triggered after the reception of the third byte is completed; at the same time, SCI3 completes the reception of the fourth byte and caches it in RXBUF;

2. Start the second data interaction with the external device: before the external device starts to send back data, DMA immediately reads the last byte of the previous frame data cached in SCI3 RXBUF; then, the external device starts to send back 4 bytes; when 3 bytes are returned, the DMA triggers the reception completion interrupt because it has read 1+3=4 bytes; the 4th byte of the response data is received by SCI3 and cached in RXBUF;

3. The above interaction process is executed repeatedly, but the sending and receiving parties can never be synchronized and are always offset by one byte;

4. Try to perform an RXBUF read operation before DMA interaction, and try to clear the possible residual data of RXBUF in advance to avoid affecting this DMA reception, but it has no effect;

Please tell me how this abnormality occurs?

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Thanks & Regards

  • Hi Yale,

    The above interactive process is executed 128 times per second, and works normally in most cases, but sometimes the following exceptions occur:

      So most of the time, it works, correct?

      Are you getting any error in the SCI module when misalignment happened? For example, do you have an overrun error?

     Do you have other DMA channels other than these two SCI3 channels?

      Can you make RX channel higher priority than the TX channel? Will that make a difference?

      For experiment, will it be out of sync if you slow down the incoming data from 128 times/s to 64 times/s?

      What might have happened is that DMA  received the RX DMA request from SCI too fast. Meaning that DMA might have receive the DMA request  for the 4th byte before it is even able to read the 3rd byte. But his is just a guess. 

  • HiYale,

      I have not heard back from you. Not sure if you are able to resolve the issue. I will close the thread for now. If you have any update you can write back to the post and the post will change the status to OPEN again.