AM263P4: Multicore Sleep

Sudhakar Elumalai Dhanasekar

Part Number: AM263P4

Hi,

Currently I've a Multicore application,

In core0, when button is pressed will go sleep(standby mode), and when again button is pressed core0 will wakeup. (I've configured button press as a external interrupt). And in other cores(core1, core2, & core 3) three GPIO pin for each core is toggled for every 0.5sec.

1. When core 0 going to sleep remaining cores(core1c core2 & core3) also needs to go to sleep and similarly for wakeup, when core0 is wakeup. Is it achievable ? If yes, how can we achieve it.

Thanks

over 1 year ago

0 Aakash Kedia over 1 year ago

TI__Mastermind 25995 points

Hi Sudhakar Elumalai Dhanasekar,

The device does not inherently supports low power mode. But it is achievable by configuring the clocks in software during runtime to enable low power mode.

What is magnitude of power consumption you are looking for in case of "low power mode" ?

Best Regards,
Aakash

0 Sudhakar Elumalai Dhanasekar over 1 year ago in reply to Aakash Kedia

Prodigy 195 points

Hi Aakash,

Currently I achieving the sleep by
a. Clock gate for unused clocks
b. Power off the unused ram banks
c. Executing wfi instruction

The core power consumption is going from 0.85W to 0.5W. This is the magnitude diff I was getting. Whether can we reduce to further ?

But my actual doubt is question 1.

0 Aakash Kedia over 1 year ago in reply to Sudhakar Elumalai Dhanasekar

TI__Mastermind 25995 points

Hi Sudhakar Elumalai Dhanasekar ,

Do you have any use case of executing WFI at 400MHz ? If not, then you can shift the CPU to lower frequency clock like RCM10 and disable the Core PLLs as well.

Depending on the Peripheral PLL usage you can choose to disable the Peripheral PLL as well.

I hope this helps.

Best Regards,
Aakash

0 Sudhakar Elumalai Dhanasekar over 1 year ago in reply to Aakash Kedia

Prodigy 195 points

Hi Aakash,

1. Under which register section I can find Core and Peripheral PLL's disable registers ?

2. In runtime is it okay to switch the core clock source from higher frequency to RCM10 ?

0 Aakash Kedia over 1 year ago in reply to Sudhakar Elumalai Dhanasekar

TI__Mastermind 25995 points

Hi Sudhakar Elumalai Dhanasekar,

You can gate the PLL Input clock with a function like this - SOC_rcmCoreApllRelockPreRequisite in source/drivers/soc/am263px/soc_rcm.c

You will find similar function in case Peripheral PLL as well.

I hope this helps.

Best Regards,
Aakash

0 Sudhakar Elumalai Dhanasekar over 1 year ago in reply to Aakash Kedia

Prodigy 195 points

Hi Aakash,

I checked the API, it seems it is not Clock Gate API for the peripheral PLL clock. Could you please provide additional details to how to disable peripheral and core PLL, It'll be more helpfull

0 Sudhakar Elumalai Dhanasekar over 1 year ago in reply to Aakash Kedia

Prodigy 195 points

Sudhakar Elumalai Dhanasekar said:
1. When core 0 going to sleep remaining cores(core1c core2 & core3) also needs to go to sleep and similarly for wakeup, when core0 is wakeup. Is it achievable ? If yes, how can we achieve it.

Kindly share some insights on this as well

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AM263P4: Multicore Sleep