Other Parts Discussed in Thread: HALCOGEN, TMDSRM48HDK, TMS570LC4357
Hey Hercules team,
I have a customer evaluating the RM57L843 for a new design and we were hoping you could provide some guidance and advice on some questions pertaining to the HALCoGen IDE. Please see a summary of our inquiries below!
Summary of Questions:
We are running into some trouble porting our existing codebase from the previous RM48 chip (RM48L952ZWT) to a new one (RM57L843BZWTT). We generated unique HALCoGen files for our RM48-based board about 10 years ago. Trying to reuse these HALCoGen files or generate new ones for RM48/57 development boards has been problematic.
- Our existing CPU uses an RM48L952ZWT chip and about 2MB of external SRAM (via EMIF ASYNC1) and 2MB of external MRAM (via EMIF ASYNC2). I am trying to port our existing application onto a TMDSRM48HDK development kit, and this application’s linker points to (and needs all of) that external RAM. Does the development kit have external ASYNC1 and ASYNC2 RAM, or are the EMIF ASYNC1 and ASYNC2 interfaces just pointing to non-existent hardware?
- If ASYNC1 and ASYNC2 RAM are unavailable, it looks like the development kit does come with 16MB of external SDRAM. Do you have any documentation for properly configuring EMIF SDRAM (the SDRAM chip on the dev board is an IS42S16400J-7BL). I ask because I am having trouble reading and writing to it.
Please let us know if you need any further clarifications on the comments and questions above in order to provide feedback!
Best regards,
Matt Calvo