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AM263P4: AM263P4 power up sequence before POR

Saurabh Kapoor
Intellectual 1230 points
Part Number: AM263P4

I was going through the 1.2V and 3.3V power circuits and power-good signal generation in the hardware design guide.

I have two doubts regarding the AM263P4 power up.

 

  1. Can we give power to the digital pins of the uC before PORZ reset is active high?
  2. Before we give PORZ active high, is there any sequence to be followed while powering up 1.2V and 3.3V? I mean should we power up 1.2V then 3.3V? 

P.S. as per the hardware design guide all PG signals are given through the AND gate:

  • 0
    TI__Guru*** 135025 points

    Hello Saurabh,

    Saurabh Kapoor said:
    Can we give power to the digital pins of the uC before PORZ reset is active high?

    I will need to follow up with another power expert tomorrow, but my understanding is that as long as the VDDS33 supply has been powered to 3.3V, then you can give power to the digital IO. The risk of device damage comes if the digital pins are powered before VDDS33 which would violate the absolute max spec for IO Pin Steady State Voltage.

    Saurabh Kapoor said:
    Before we give PORZ active high, is there any sequence to be followed while powering up 1.2V and 3.3V? I mean should we power up 1.2V then 3.3V?

    No, per Section 6.11.2.1 Power-On and Reset Sequencing of the device datasheet: There is no sequencing requirement with respect to the primary core digital VDD 1.2V and I/O power 3.3V rails. I can look if we need to add this clarification into the HW design guide as well.

    Best Regards,

    Ralph Jacobi

  • 0
    TI__Guru*** 135025 points

    Hello Saurabh,

    Confirmed that for standard IO pins the key spec to follow is the VDDS33 + 0.3V absolute max spec, as long as that is followed then you can put active high on IO regardless of state of PORZ.

    Best Regards,

    Ralph Jacobi