Other Parts Discussed in Thread: SYSCONFIG
How to configure RTI module?
2634's RTI module confuses me.
Firstly, I modified RTI_LED_BLINK example to make sure LED blinks forever.
System_init(); Board_init(); rti_led_blink(NULL); while(1); // Board_deinit(); // System_deinit(); return 0;
DebugP_log("[RTI LED Blink Test] Timer Started...\r\n"); // /* Wait until the LED is blinked specified number of times */ // while(gBlinkCount < LED_BLINK_COUNT); // // /* Stop the RTI counter */ // (void)RTI_counterDisable(CONFIG_RTI0_BASE_ADDR, RTI_TMR_CNT_BLK_INDEX_0); // // DebugP_log("[RTI LED Blink Test] Timer Stopped...\r\n"); // // DebugP_log("All tests have passed!!\r\n"); // // Board_driversClose(); // Drivers_close();
Then I configure syscfg:
set clock source to SYS_CLK, input clock frequency to 200M
set RTI input clock source to SYS_CLK, input clock frequency to 200M
set Counter Block 0 desired output frequency to 100M, the actual output frequency is 100M.(like step 1, set divide to 2)
set compare event 0 tick period (usecs) to 1M, the actual tick period is 1M.
I run the code, the LED toggles every 1s, when I see the registers, FRC0 is constantly increasing, UC0 is range in 0-199999, CPUC0 = 199999, CMP0 is constantly increasing and almost equals to FRC0
When I set Counter Block 0 desired output frequency to 2M, the actual output frequency is 2M,compare event 0 tick period (usecs) remain to 1M
I run the code, the LED toggles every 1s, FRC0 is constantly increasing, UC0 is range in 0-199999, CPUC0 = 199999, CMP0 is constantly increasing and almost equals to FRC0
When I set compare event 0 tick period (usecs) to 2M, others unchanged
I run the code, the LED toggles every 2s, FRC0 is constantly increasing, UC0 is range in 0-199999, CPUC0 = 199999, CMP0 is constantly increasing and almost equals to FRC0
so what means of register FRC0 CMP0 UC0 CPUC0, How to associate these registers with syscfg desired output frequency and tick period(usesc)?
Besides, how do I configure RTI registers like C2000 to timing code runtime?(CCS just set clock divide, PRD, read CNT)