MCU-PLUS-SDK-AM263PX: “ICSS-EMAC Lwip Example” on TMDSCNCD263P-AM263Px Sitara Control Card

TollMan

Part Number: MCU-PLUS-SDK-AM263PX
Other Parts Discussed in Thread: DP83869

Tool/software:

I am using AM263Px MCU+ SDK 09.02.00 “ICSS-EMAC Lwip Example” on TMDSCNCD263P-AM263Px Sitara Control Card. I want to test that a PC connected through an unmanaged layer 2 switch (TL-SG105) can communicate with the Control Card.

I modified only the line of code here:

#define LWIP_PORT_INIT_IPADDR(addr) IP4_ADDR((addr), 192,168,0,200)

… to:

#define LWIP_PORT_INIT_IPADDR(addr) IP4_ADDR((addr), 192,168,1,254)

... to change the IP address of the Control Card to that of my PC.

On the PC, I am running Wireshark.

I also see in the documentation that I ping is enabled. I am sending a ping request from the PC while the SDK example is running.

Note:

Enet Lwip TCP Client Example works with the same setup. I see DHCP Discover packets on Wireshark.

Questions/Issues:

So far, I am not able to ping the Control Card.

If anything below does not point to a solution, please suggest troubleshooting steps.

What is the switch configuration needed for SW14, SW15, and SW16? I have all switches open, but I am not certain this is correct.

Although I verified that a breakpoint can be hit at:

print_cpu_load();

… I see no printf on the console.

I tried running in debug mode in both DEV_BOOT mode, and with SBL_NULL.

The Console outputs are below:

====================================

SBL_NULL

====================================

Cortex_R5_0: GEL Output: Gel files loading on R5F0 Complete

Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.

Please Wait...

Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched

Cortex_R5_0: GEL Output: Crystal Clock present

Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched

Cortex_R5_0: GEL Output: SOP MODE = 0x00000003

Cortex_R5_0: GEL Output:

OSPI - 8S Functional boot mode

Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched

Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA

Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched

Cortex_R5_0: GEL Output: r5fss0 = 0x00000001

Cortex_R5_0: GEL Output: r5fss1 = 0x00000000

Cortex_R5_0: GEL Output:

R5FSS0 is in Dual core mode

Cortex_R5_0: GEL Output:

R5FSS1 is in Dual core mode

Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked

Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked

Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked

Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked

Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked

Cortex_R5_0: GEL Output:

*** R5FSS0 Reset DualCore ***

Cortex_R5_0: GEL Output:

***R5FSS1 Reset DualCore ***

Cortex_R5_0: GEL Output: R5F ROM Eclipse

Cortex_R5_0: GEL Output: R5FSS0_0 Released

Cortex_R5_0: GEL Output: R5FSS0_1 Released

Cortex_R5_0: GEL Output: R5FSS1_0 Released

Cortex_R5_0: GEL Output: R5FSS1_1 Released

Cortex_R5_0: GEL Output: L2 Mem Init Complete

Cortex_R5_0: GEL Output: MailBox Mem Init Complete

Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********

Cortex_R5_0: GEL Output: In ROM Setting Mode

Cortex_R5_0: GEL Output: Switch to XTAL Complete

Cortex_R5_0: GEL Output: CORE PLL Configuration Complete

Cortex_R5_0: GEL Output: SYS_CLK DIVBY2

Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs

Cortex_R5_0: GEL Output:

CLK Programmed R5F=400MHz and SYS_CLK=200MHz

Cortex_R5_0: GEL Output:

*** Enabling Peripheral Clocks ***

Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks

Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks

Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks

Cortex_R5_0: GEL Output: Enabling QSPI Clocks

Cortex_R5_0: GEL Output: Enabling I2C Clocks

Cortex_R5_0: GEL Output: Enabling TRACE Clocks

Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks

Cortex_R5_0: GEL Output: Enabling MMCSD Clocks

Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks

Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks

Cortex_R5_0: GEL Output: Enabling CPTS Clocks

Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks

Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks

Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks

Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

====================================

DEV_BOOT

====================================

Cortex_R5_0: GEL Output: Gel files loading on R5F0 Complete

Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched.

Please Wait...

Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched

Cortex_R5_0: GEL Output: Crystal Clock present

Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched

Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B

Cortex_R5_0: GEL Output:

DevBoot mode

Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched

Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA

Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched

Cortex_R5_0: GEL Output: r5fss0 = 0x00000101

Cortex_R5_0: GEL Output: r5fss1 = 0x00000100

Cortex_R5_0: GEL Output:

R5FSS0 is in Lockstep mode

Cortex_R5_0: GEL Output:

R5FSS1 is in Lockstep mode

Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked

Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked

Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked

Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked

Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked

Cortex_R5_0: GEL Output:

*** R5FSS0 Reset DualCore ***

Cortex_R5_0: GEL Output:

***R5FSS1 Reset DualCore ***

Cortex_R5_0: GEL Output: R5F ROM Eclipse

Cortex_R5_0: GEL Output: R5FSS0_0 Released

Cortex_R5_0: GEL Output: R5FSS0_1 Released

Cortex_R5_0: GEL Output: R5FSS1_0 Released

Cortex_R5_0: GEL Output: R5FSS1_1 Released

Cortex_R5_0: GEL Output: L2 Mem Init Complete

Cortex_R5_0: GEL Output: MailBox Mem Init Complete

Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured********

Cortex_R5_0: GEL Output: In ROM Setting Mode

Cortex_R5_0: GEL Output: Switch to XTAL Complete

Cortex_R5_0: GEL Output: CORE PLL Configuration Complete

Cortex_R5_0: GEL Output: PER PLL Configuration Complete

Cortex_R5_0: GEL Output: SYS_CLK DIVBY2

Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs

Cortex_R5_0: GEL Output:

CLK Programmed R5F=400MHz and SYS_CLK=200MHz

Cortex_R5_0: GEL Output:

*** Enabling Peripheral Clocks ***

Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks

Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks

Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks

Cortex_R5_0: GEL Output: Enabling QSPI Clocks

Cortex_R5_0: GEL Output: Enabling I2C Clocks

Cortex_R5_0: GEL Output: Enabling TRACE Clocks

Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks

Cortex_R5_0: GEL Output: Enabling MMCSD Clocks

Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks

Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks

Cortex_R5_0: GEL Output: Enabling CPTS Clocks

Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks

Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks

Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks

Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

====================================

Regards,

Tollman

9 months ago

0 BrandonAzbell 9 months ago

TI__Guru 63830 points

Additional information:

The address of my PC is 192.168.1.3. The PC is a client.

The address of the EVK is 192.168.1.254.

0 TollMan 9 months ago

Intellectual 445 points

UPDATE

I spend additional time reviewing the SDK example testing. This resulted in more questions.

I do not have an:

DP83826-EVM-AM2 Evaluation board | TI.com

… plug in board yet.

4a) Question:

What functionality in the example require this board to be connected?

4b) Question:

What functions does the on-board RJ-45 support? e.g. Can I use this port to (ICMP) ping from the PC?

5) Question:

I tried to send UDP packets to the Control Card from the PC. I see in Wireshark that this results in an ARP request. This is expected. However, I see no reply from the Control Card.

Also, when I look at the lwip_stats struct before and after sending the packets, I see no change in any value.

See image:

Is it safe to assume that the Control Card is not able to receive Ethernet communications through the on-board RJ-45 port?

6) Question:

I noticed when I send UDP from the PC (corresponding to the ARP Requests) that the green LED flashes on the Control Card. This makes me think that the PHY is receiving the packets, but they are being dropped before making it up to LwIP.

Do you agree with this assessment?

7) Note:

I also tried using ipref3 on the PC, but as expected, the connection fails when I execute:

> iperf -c 192.168.1.254 -i 5 -t 20 -d

This command is based on the documentation here:

AM263Px MCU+ SDK: ICSS-EMAC Lwip Example (ti.com)

This is also generating a failed ARP request.

Regards,

Tollman

0 TollMan 9 months ago

Intellectual 445 points

UPDATE:

The issue with the printf() not functioning was resolved. For some reason the SysConfig->Debug Log -> Enable CCS Log was not enabled for this project.

0 Nilabh Anand 9 months ago in reply to TollMan

TI__Mastermind 34962 points

Hi TollMan,

TollMan said:
The issue with the printf() not functioning was resolved. For some reason the SysConfig->Debug Log -> Enable CCS Log was not enabled for this project.

You can see the CPU load printed on UART Terminal.

e2e.ti.com/.../code-composure-studio-serial-terminal

0 TollMan 9 months ago in reply to Nilabh Anand

Intellectual 445 points

Hi Nilabh,

The printf() is helpful for diagnosing, and solves issue 3), but I still have not successfully communicated with the EKV using:

AM263Px MCU+ SDK 09.02.00 “ICSS-EMAC Lwip Example

Please review issues 1), 2), 4), 5), 6), and 7).

Thanks,

Tollman

0 Nilabh Anand 9 months ago in reply to TollMan

TI__Mastermind 34962 points

Hi TollMan,

We are able to see the AM263Px link up and able to ping it also

ping 192.168.0.200

Pinging 192.168.0.200 with 32 bytes of data:
Reply from 192.168.0.200: bytes=32 time=2ms TTL=255
Reply from 192.168.0.200: bytes=32 time=1ms TTL=255
Reply from 192.168.0.200: bytes=32 time=1ms TTL=255
Reply from 192.168.0.200: bytes=32 time=1ms TTL=255

Ping statistics for 192.168.0.200:
Packets: Sent = 4, Received = 4, Lost = 0 (0% loss),
Approximate round trip times in milli-seconds:
Minimum = 1ms, Maximum = 2ms, Average = 1ms

NULL Bootloader Execution Complete...
INFOMII mode
load to PRU0 passed
load to PRU1 passed
Starting lwIP, local interface IP is 192.168.0.200
[LWIPIF_LWIP]Link is down[LWIPIF_LWIP] Interface layer handle is Initialised
[LWIPIF_LWIP] NETIF INIT SUCCESS
status_callback==UP, local interface IP is 192.168.0.200
UDP server listening on port 5001
link_callback==UP
6. 36s : CPU load = 0.73 %
11. 36s : CPU load = 0.60 %
16. 36s : CPU load = 0.58 %
21. 36s : CPU load = 0.56 %
26. 36s : CPU load = 0.56 %
31. 36s : CPU load = 0.56 %
36. 36s : CPU load = 0.56 %

0 Nilabh Anand 9 months ago in reply to Nilabh Anand

TI__Mastermind 34962 points

I am using SDK 9.2 and using the device in SBL null boot mode(SOC initialization binary

AM263Px MCU+ SDK: Additional Details

Also I am using only single port RJ45 as I also do not have the EVM mentioned above.

TollMan said:
What is the switch configuration needed for SW14, SW15, and SW16? I have all switches open, but I am not certain this is correct.

This is wrong,please refer to the user guide of AM263Px CC section 2.16 for more details on switch configuration

www.ti.com/.../spruj86b.pdf

0 TollMan 9 months ago in reply to Nilabh Anand

Intellectual 445 points

Hi Nilabh,

Regarding:

"This is wrong,please refer to the user guide of AM263Px CC section 2.16 for more details on switch configuration"

I reviewed the User's Guide. I'm posting this prior to comparing to the schematic for the sake of a rapid response.

Looking at Table 2-16 I think I should probably be closing SW15 (to pull high ICSSM2_MUX_SEL high).

I tried to ping again from the connected PC, but I see the same symptoms:

a) ping response is "destination unreachable"

b) on Wireshark I see no response to the ARP Broadcast.

From the AM263Px I see the following printf:

[Cortex_R5_0] MII mode
load to PRU0 passed
load to PRU1 passed
Starting lwIP, local interface IP is 192.168.1.254
[LWIPIF_LWIP]Link is Up on port 1
[LWIPIF_LWIP] Interface layer handle is Initialised
[LWIPIF_LWIP] NETIF INIT SUCCESS
status_callback==UP, local interface IP is 192.168.1.254
UDP server listening on port 5001
link_callback==UP
6. 27s : CPU load = 0.97 %
11. 27s : CPU load = 0.73 %
16. 27s : CPU load = 0.72 %
21. 27s : CPU load = 0.73 %
26. 27s : CPU load = 0.72 %
31. 27s : CPU load = 0.73 %
36. 27s : CPU load = 0.74 %
41. 27s : CPU load = 0.74 %
46. 27s : CPU load = 0.74 %
51. 27s : CPU load = 0.73 %
56. 27s : CPU load = 0.73 %
61. 27s : CPU load = 0.75 %
66. 27s : CPU load = 0.73 %
71. 27s : CPU load = 0.73 %
76. 27s : CPU load = 0.75 %
81. 27s : CPU load = 0.74 %

I will continue to troubleshoot, but I am sending this now hoping you will rapidly see my mistake.

Regards,

Tollman

0 Nilabh Anand 9 months ago in reply to TollMan

TI__Mastermind 34962 points

What is your PC IP address? Also can you try to ping by directly connecting EVM to PC by removing the switch?(Just to eliminate any extra variable)

0 TollMan 9 months ago in reply to Nilabh Anand

Intellectual 445 points

I tried connecting directly to the PC at IP address 192.168.1.3.

Upon making this change I see in the printf:

link_callback==DOWN
196. 27s : CPU load = 0.76 %
201. 27s : CPU load = 0.75 %
206. 27s : CPU load = 0.76 %
211. 27s : CPU load = 0.74 %
link_callback==UP
216. 27s : CPU load = 0.78 %
221. 27s : CPU load = 0.76 %
226. 27s : CPU load = 0.75 %
231. 27s : CPU load = 0.75 %
236. 27s : CPU load = 0.76 %
241. 27s : CPU load = 0.74 %
246. 27s : CPU load = 0.75 %
251. 27s : CPU load = 0.75 %
256. 27s : CPU load = 0.75 %
261. 27s : CPU load = 0.75 %
266. 27s : CPU load = 0.75 %

However, when I ping, or send other UDP I have the same results. I only see ARP Broadcast with no response.

The RJ-45 LED flashes upon transmits from the PC.

Breakpoints here:

mcu_plus_sdk_am263px_09_02_00_56\source\networking\icss_emac\lwipif\src\lwip2lwipif.c

...in these functions get hit:

.. once upon reset:

static int LWIPIF_LWIP_start(struct netif *netif)

.. periodically:

static void LWIPIF_LWIP_poll(void *arg0)

.. never:

static err_t LWIPIF_LWIP_send(struct netif *netif,

struct pbuf *p)

.. never:

void LWIPIF_LWIP_input(struct netif *netif,

struct pbuf *hPbufPacket)

Can you confirm that SW15 should be closed?

0 TollMan 9 months ago in reply to TollMan

Intellectual 445 points

...

4) Also, is it true that a breakpoint here should get hit:

mcu_plus_sdk_am263px_09_02_00_56\source\networking\icss_emac\source\icss_emac.c

void ICSS_EMAC_rxInterruptHandler(void *args)

0 TollMan 9 months ago in reply to TollMan

Intellectual 445 points

...

4b) Can you confirm that, assuming correct

switch/jumper configuration, PHY configuration, link partner configuration, Ethernet connection,

... the function:

mcu_plus_sdk_am263px_09_02_00_56\source\networking\icss_emac\source\icss_emac.c

void ICSS_EMAC_rxInterruptHandler(void *args)

... will execute.

I want to rule a switch/jumper configuration mistake. Please check:

... and let me know it there is any other image that would be helpful.

Regards,

Tollman

0 TollMan 9 months ago in reply to TollMan

Intellectual 445 points

...

And here is what I see in Wireshark (capturing the Ethernet network interface) when I ping, or try to send a UDP datagram from the PC:

Note the lack of response despite the green LED on the RJ-45 blinking.

0 TollMan 9 months ago in reply to TollMan

Intellectual 445 points

5b)

It occurred to me that perhaps I've been focusing on switches, but the issue may be the resistor jumpers (POP/DNI):

Is it true that I need to modify my EVK for this to work?

0 Nilabh Anand 8 months ago in reply to TollMan

TI__Mastermind 34962 points

Is there any changes in your syscfg as compared to in the default example(I have shared the pic of my configuration which is the Out of box configuration also).

0 Nilabh Anand 8 months ago in reply to TollMan

TI__Mastermind 34962 points

TollMan said:
4b) Can you confirm that, assuming correct

switch/jumper configuration, PHY configuration, link partner configuration, Ethernet connection,

... the function:

mcu_plus_sdk_am263px_09_02_00_56\source\networking\icss_emac\source\icss_emac.c

void ICSS_EMAC_rxInterruptHandler(void *args)

... will execute.

Yes this is true, this Rx _interrupt handler will get hit.

0 Nilabh Anand 8 months ago in reply to Nilabh Anand

TI__Mastermind 34962 points

TollMan said:
I want to rule a switch/jumper configuration mistake. Please check:

... and let me know it there is any other image that would be helpful.

Can you put SW15 to OFF and try?

0 TollMan 8 months ago in reply to Nilabh Anand

Intellectual 445 points

Hi Nilabh,

As suggested, I changed SW15 to off (back to the original position), and re-tested. After doing so, I see the same results. Namely, when I ping from the PC, I see:

* ARP requests in Wireshark upon PING.

* ICSS_EMAC_rxInterruptHandler() breakpoint is not hit upon PING.

Please confirm:

The Control Card switch/jumper configuration should be configured such that "PRU0 MII0" is routed to "On-board PH" for this test as highlighted here:

Regards,

Tollman

0 Nilabh Anand 8 months ago in reply to TollMan

TI__Mastermind 34962 points

Hi Tollman,

Now things are pointing towards a faulty board.I am sharing pic of my board. If everything is same on your board too, Can you try with a different board
?

0 TollMan 8 months ago in reply to Nilabh Anand

Intellectual 445 points

Hi Nilabh,

I tried a second Control Card. All switches SW14, SW15, SW16 open. Direct connection (no switch in between).

Same results. Link, but no communication.

+1 TollMan 8 months ago in reply to TollMan

Intellectual 445 points

I am re-testing my setup with the new Control Card, by running loopback, and CPSW examples. I'll let you know if these tests pass.

0 TollMan 8 months ago in reply to TollMan

Intellectual 445 points

I am running the "enet_loopback_am263px-cc_r5fss0-0_freertos_ti-arm-clang" SDK example on the second Control Card, and see suspicious results.

The MAC loopback looks good:

-----------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------

[Cortex_R5_0]
0: Internal MAC loopback
1: External PHY loopback

Enter option: =============================
Enet Loopback: Iteration 1
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2
PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets
Delete EnetApp_txTask() and exit..

Port 0 Statistics
-----------------------------------------
rxGoodFrames = 5000
rxBcastFrames = 5000
rxOctets = 2590000
txGoodFrames = 5000
txBcastFrames = 5000
txOctets = 2590000
octetsFrames512to1023 = 10000
netOctets = 5180000
txPri[0] = 5000
txPriBcnt[0] = 2590000

Port 1 Statistics
-----------------------------------------
rxGoodFrames = 5000
rxBcastFrames = 5000
rxOctets = 2590000
txGoodFrames = 5000
txBcastFrames = 5000
txOctets = 2590000
octetsFrames512to1023 = 10000
netOctets = 5180000
txPri[0] = 5000
txPriBcnt[0] = 2590000

RX Channel Statistics
-----------------------------------------
Data Notify Count = 316
Total Packets Count = 5032
Packets per Notify Max = 16
Packets per Notify[0] = 16
Packets per Notify[1] = 8
Data Notify Count = 316
Zero Notify Count = 1
Total Packets Count = 5000
Packets per Notify Max = 16
Packets per Notify[0] = 16
Packets per Notify[1] = 8
RX Submit Packet EnQ count = 5032
RX Submit Packet DeQ count = 5000
TX Channel Statistics
-----------------------------------------
Data Notify Count = 315
Total Packets Count = 5000
Packets per Notify Max = 16
Packets per Notify[0] = 8
Packets per Notify[1] = 16
Data Notify Count = 315
Total Packets Count = 5000
Packets per Notify Max = 16
Packets per Notify[0] = 8
Packets per Notify[1] = 16
TX Submit Packet EnQ count = 5000
TX Submit Packet DeQ count = 5000
Cpsw_handleLinkDown: Port 2: Link down

Test complete: PASS
=============================
Enet Loopback: Iteration 2
=============================

-----------------------------------------------------------------------------------------------

</printf1>

-----------------------------------------------------------------------------------------------

However, the PHY loopback does not seem to work

-----------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------

[Cortex_R5_0]
0: Internal MAC loopback
1: External PHY loopback

Enter option: =============================
Enet Loopback: Iteration 1
=============================
CPSW_3G Test
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2
EnetPhy_bindDriver: PHY 0: OUI:080028 Model:0f Ver:03 <-> 'dp83869' : OK

PHY 0 is alive
initQs() txFreePktInfoQ initialized with 16 pkts
Cpsw_handleLinkUp: Port 2: Link up: 100-Mbps Full-Duplex

-----------------------------------------------------------------------------------------------

</printf2>

-----------------------------------------------------------------------------------------------

Do you agree?

What SW14, SW15 SW16 positions need to be configured for the PHY loopback?

0 TollMan 8 months ago in reply to TollMan

Intellectual 445 points

Hi Nilabh,

I did some additional testing with "Enet CPSW Loopback Example" on PCB #2.

I found that some packets are being dropped during the PHY Loopback.

I halt the processor after a few seconds aan see it is looping in the loop:

while (txRetrievePktCnt != txCnt) {...}

It appears that "Enet CPSW Loopback Example" is using "PHY 0"

... corresponding to RGMII2 (P0_PRU0):

... and with my current hardware configuration:

SW14 open

SW15 open

SW16 open

... should be routed to the On-board PHY.

This loopback test seems to indicate that, although there are dropped packets, the PHY is functional, and the MAC to PHY (RGMII2) is functional.

Do you agree with this analysis?

Can you try "Enet CPSW Loopback Example" on your Control Card? Do you also see dropped packets?

Regards,

Tollman

0 TollMan 8 months ago in reply to TollMan

Intellectual 445 points

Hi Nilabh,

To test my setup, I swapped in an AM263x Control Card (the older, 3 RJ-45, non-P version).

I successfully ran the TCP Client SDK example modified for static IP address.

Here is the Wireshark log showing the successful:

ARP request
ARP response
TCP connection attempt and retry.

Note: The TCP connection attempt failure was expected; I didn't have the server running.

I tried the AM263Px version of the project. This was not successful.

Do you have any troubleshooting ideas?

Regards,

Tollman

0 Nilabh Anand 8 months ago in reply to TollMan

TI__Mastermind 34962 points

Hi Tollman,

Apologies for the delay, I was on leave for few days.

TollMan said:
I tried the AM263Px version of the project. This was not successful.

Do you have any troubleshooting ideas?

This is with CPSW example correct?

Arm-based microcontrollers

Arm-based microcontrollers forum

MCU-PLUS-SDK-AM263PX: “ICSS-EMAC Lwip Example” on TMDSCNCD263P-AM263Px Sitara Control Card