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TMS570LS3137: When the coprocessor is used to output PWM, the waveform is inaccurate

Part Number: TMS570LS3137

Tool/software:

Hello, I use the TMS570LS3137 coprocessor to output PWM waveform, the code is as follows:

  1. L01   PWCNT { next=L02,hr_lr=LOW,cond_addr=L02,en_pin_action=ON,pin=20,action=PULSEHI,reg=NONE,data=0};
  2. L02   DJZ { next=PWM_IN_Duty1,cond_addr=L03,reg=NONE,data=0};
  3. L03   MOV64 { next=L04,remote=L01,en_pin_action=ON,cond_addr=L02,pin=20,comp_mode=ECMP,action=PULSEHI,reg=NONE,irq=ON,data=0};
  4. L04   MOV64 { next=PWM_IN_Duty1,remote=L02,en_pin_action=ON,cond_addr=L03,pin=20,comp_mode=ECMP,action=CLEAR,reg=NONE,irq=ON,data=0};

Under normal circumstances, this output PWM is no problem, but I found that if the main processor is changing the output of other HET pins (such as the main processor changes the output of HET4 and HET7 pins, and the coprocessor outputs PWM through HET20 pins), the output PWM will be incorrect at this time. I experimented with the following code (coprocessor code unchanged) :

  1. drvSetABSyn((FLOAT32)0.5, 700U);
  2. drvSoftwareDelaySomeMs(10000U);
  3. while(1)
  4. {
  5.     hetREG1->DOUT &= (uint32)(~(((uint32)1U) << 4));
  6.     hetREG1->DOUT |= ((uint32)1U) << 7;
  7.     hetREG1->DOUT |= ((uint32)1U) << 4;
  8.     hetREG1->DOUT &= (uint32)(~(((uint32)1U) << 7));
  9. }

The first line by modifying the coprocessor's memory output duty cycle of 50%, frequency of 700HZ PWM waveform, the second line delay 10 seconds, and then cycle control of the fourth and seventh pins of the HET. The final output is as follows:

Where the yellow line is the PWM waveform output by the HET20 pin, it can be clearly seen that the waveform is no problem before the main processor controls the HET pin, and the PWM is abnormal after the control.

What is the reason for this phenomenon? What's the solution?

  • Hi Liu Peng,

    hetREG1->DOUT &= (uint32)(~(((uint32)1U) << 4));

    Maybe you are thinking like the above instruction will only affect the HET4 right?

    Actually, the above instruction will affect all HET pins. I mean the above instruction will write 0 on the HET4 and 1 on all other HET pins.

    I mean for example assume HET20 is generating a PWM waveform, and this pin is at logic-low just before you are executing this instruction, and if processor executes this instruction, it will immediately pull the HET20 to the logic-high forcefully. So, this will mean to change the waveform right, i mean duty cycle will also get changes right?

    • hetREG1->DOUT |= ((uint32)1U) << 7;
    •     hetREG1->DOUT |= ((uint32)1U) << 4;
    •     hetREG1->DOUT &= (uint32)(~(((uint32)1U) << 7));

    Similarly, these instructions will also change the HET20 waveform.

    So, in these kinds of situations you should not use DOUT register, instead of it would be better to use the HETDSET (to set a pin) and HETDCLR (to clear a pin) registers.

    So, example if you see HETDSET register:

    The bits you write 1 in this will only get set and remaining bits state will be unchanged.

    Similarly, for HETCLR register the bits you write 1 will get clear and all the remaining bits will be unchanged.

    --
    Thanks & regards,
    Jagadish.

  • hetREG1->DOUT &= (uint32)(~(((uint32)1U) << 4));

    The above code has the same meaning as the following code

    hetREG1->DOUT =  hetREG1->DOUT & (uint32)(~(((uint32)1U) << 4));

    This code reads the state of the hetREG1->DOUT register, sets BIT4 to 0, and does not modify the state of the other bits. For example, BIT20 used to be 1, and is still 1 after AND with 1.BIT20 used to be 0, and is still 0 after AND with 1.

  • Hi Liu Peng,

    This code reads the state of the hetREG1->DOUT register, sets BIT4 to 0, and does not modify the state of the other bits. For example, BIT20 used to be 1, and is still 1 after AND with 1.BIT20 used to be 0, and is still 0 after AND with 1.

    Okay, 

    However, this instruction involves Read-Modify-Write operation, right?

    What if the pin value changes after our read operation?

    I mean for example assume HET20 is at logic-0 before we read, and after we read assume, the value changed to logic-1(due to period or duty cycle time out). But we still have logic-0 and we write the same into the HET-20-bit value, but HET-20 should be logic-1 according to PWM but we are making it logic-0. 

    This kind of race around conditions will occur if the two processors working independently. So, it would be better use HETDSET and HETCLR registers, these registers won't do read modify write they will only write to the corresponding bits which are 1.

    --
    Thanks & regards,
    Jagadish.

  • I see.Thanks a million.