MCU-PLUS-SDK-AM263PX: AM263Px MCU+ SDK: ICSS-EMAC Lwip Example Transmit Error

TollMan

Intellectual 445 points

Part Number: MCU-PLUS-SDK-AM263PX
Other Parts Discussed in Thread: DP83869

Tool/software:

ICSS-EMAC Issue:

I am trying to test the SDK example:

AM263Px MCU+ SDK: ICSS-EMAC Lwip Example (ti.com)

The Control Card is connected to a PC through the on-board RJ-45 (via DP83869).

I understand that PING does not work, but I expect that the ARP request from the PC PINGing the Control Card will trigger an ARP Announcement transmission from the Control Card. However, I see no transmissions from Control Card when running ICSS-EMAC.

I am testing this with Wireshark on the PC.

Test Setup Validation:

When I execute SDK example:.

AM263Px MCU+ SDK: Enet Lwip TCP Client Example (ti.com)

… with the same IP Address, and test setup, I see ARP Announcements being transmitted by the Control Card.

Troubleshooting Steps:

I put breakpoints in icss_emac.c at, ICSS_EMAC_txPacketEnqueue(). This revealed that icss_emac transmit is executing.

I put a breakpoint in lwip2icss_emac.c at Lwip2Emac_sendTxPackets(). This breakpoint is not hit.

I see this on the console:

INFO: Bootloader_socLoadHsmRtFw:82: Device Type : HSFS

INFO: Bootloader_socLoadHsmRtFw:84: HSMRT Size in Bytes : 24739

INFO: Bootloader_socLoadHsmRtFw:97: hsm runtime firmware load complete ...

Starting NULL Bootloader ...

INFO: Bootloader_runCpu:155: CPU r5f1-1 is initialized to 400000000 Hz !!!

INFO: Bootloader_runCpu:155: CPU r5f1-0 is initialized to 400000000 Hz !!!

INFO: Bootloader_runCpu:155: CPU r5f0-1 is initialized to 400000000 Hz !!!

[BOOTLOADER_PROFILE] Boot Media : undefined

KPI_DATA: [BOOTLOADER_PROFILE] Boot Image Size : 0 KB

[BOOTLOADER_PROFILE] Cores present :

KPI_DATA: [BOOTLOADER PROFILE] System_init : 941us

KPI_DATA: [BOOTLOADER PROFILE] Drivers_open : 142us

KPI_DATA: [BOOTLOADER PROFILE] LoadHsmRtFw : 29804us

KPI_DATA: [BOOTLOADER_PROFILE] SBL Total Time Taken : 58653us

NULL Bootloader Execution Complete...

INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 400000000 Hz !!!

INFO: Bootloader_runSelfCpu:217: All done, reseting self ...

MII mode

load to PRU0 passed

load to PRU1 passed

Starting lwIP, local interface IP is 192.168.2.252

[LWIPIF_LWIP]Link is Up on port 1

[LWIPIF_LWIP] Interface layer handle is Initialised

[LWIPIF_LWIP] NETIF INIT SUCCESS

status_callback==UP, local interface IP is 192.168.2.252

UDP server listening on port 5001

link_callback==UP

6. 26s : CPU load = 0.96 %

11. 26s : CPU load = 0.73 %

16. 26s : CPU load = 0.74 %

21. 26s : CPU load = 0.72 %

26. 26s : CPU load = 0.75 %

31. 26s : CPU load = 0.75 %

36. 26s : CPU load = 0.74 %

41. 26s : CPU load = 0.74 %

46. 26s : CPU load = 0.79 %

[LWIPIF_LWIP]ERROR: Rx Pbuf_alloc() in LWIPIF_LWIP_INPUT failure.!

pbuf_free: p->ref > 0ASSERT: 46.796612s: /nightlybuilds/mcupsdk_internal/jenkins/mcu_plus_sdk_am263px_09_02_00_56/source/networking/lwip/lwip-stack/src/core/pbuf.c:pbuf_free:755: 0 failed !!!

I also see this on the console:

…

[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilaisation[LWIPIF_LWIP]Packet Dropped!: Rx callback is called before Interface layer handle initilais

I only notice the above error on the console when I halt the processor at a breakpoint. It Is possible that this causes a race condition.

Here are some expressions I captured when halted at ICSS_EMAC_txPacketEnqueue():

((ICSS_EMAC_Object *)(icssemacHandle2->object))->hostStat	struct ICSS_EMAC_HostStatistics_s[2]	[{txUcast=1,txBcast=0,txMcast=0,txOctets=64,rxUcast=0...},{txUcast=0,txBcast=0,txMcast=...]	0x700B5694
	[0]	struct ICSS_EMAC_HostStatistics_s	{txUcast=1,txBcast=0,txMcast=0,txOctets=64,rxUcast=0...}	0x700B5694
		txUcast	unsigned int	1	0x700B5694
		txBcast	unsigned int	0	0x700B5698
		txMcast	unsigned int	0	0x700B569C
		txOctets	unsigned int	64	0x700B56A0
		rxUcast	unsigned int	0	0x700B56A4
		rxBcast	unsigned int	140	0x700B56A8
		rxMcast	unsigned int	5	0x700B56AC
		rxOctets	unsigned int	10023	0x700B56B0
		rxUnknownProtocol	unsigned int	1	0x700B56B4
		txDroppedPackets	unsigned int	0	0x700B56B8
		linkBreak	unsigned int	2	0x700B56BC
		txCollisionDroppedPackets	unsigned int	0	0x700B56C0
		txNumCollision	unsigned int	0	0x700B56C4
	[1]	struct ICSS_EMAC_HostStatistics_s	{txUcast=0,txBcast=0,txMcast=0,txOctets=0,rxUcast=0...}	0x700B56C8
icssemacHandle2	struct ICSS_EMAC_Config_s *	0x70131D80 {object=0x700B1C40,attrs=0x70131A94 {emacMode=3 '\x03',phyAddr=[0,1],phyToMacInterfaceMode=...}	0x700D32C4
hostStatPtr	struct ICSS_EMAC_HostStatistics_s *	0x700B5694 {txUcast=1,txBcast=0,txMcast=0,txOctets=64,rxUcast=0...}	0x700D55D4
	*(hostStatPtr)	struct ICSS_EMAC_HostStatistics_s	{txUcast=1,txBcast=0,txMcast=0,txOctets=64,rxUcast=0...}	0x700B5694
		txUcast	unsigned int	1	0x700B5694
		txBcast	unsigned int	0	0x700B5698
		txMcast	unsigned int	0	0x700B569C
		txOctets	unsigned int	64	0x700B56A0
		rxUcast	unsigned int	0	0x700B56A4
		rxBcast	unsigned int	140	0x700B56A8
		rxMcast	unsigned int	5	0x700B56AC
		rxOctets	unsigned int	10023	0x700B56B0
		rxUnknownProtocol	unsigned int	1	0x700B56B4
		txDroppedPackets	unsigned int	0	0x700B56B8
		linkBreak	unsigned int	2	0x700B56BC
		txCollisionDroppedPackets	unsigned int	0	0x700B56C0
		txNumCollision	unsigned int	0	0x700B56C4
txQueue	struct ICSS_EMAC_QueueParams_s *	0x700B5A9C {qStat={rawCount=1,errCount=0},buffer_offset=34144,buffer_desc_offset=...	0x700D55D8
	*(txQueue)	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=1,errCount=0},buffer_offset=34144,buffer_desc_offset=5292,queue_desc_offset=...	0x700B5A9C
		qStat	struct ICSS_EMAC_QueueStats	{rawCount=1,errCount=0}	0x700B5A9C
			rawCount	unsigned int	1
			errCount	unsigned int	0
		buffer_offset	unsigned short	34144	0x700B5AA4
		buffer_desc_offset	unsigned short	5292	0x700B5AA6
		queue_desc_offset	unsigned short	7860	0x700B5AA8
		queue_size	unsigned short	5680	0x700B5AAA
lwip_stats	struct stats_	{link={xmit=0,recv=0,fw=0,drop=0,chkerr=0...},etharp={xmit=1,recv=67,fw=0,drop=1,chkerr=...,ip_frag=...	0x700D15B8
	link	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D15B8
	etharp	struct stats_proto	{xmit=1,recv=67,fw=0,drop=1,chkerr=0...}	0x700D15D0
		xmit	unsigned short	1	0x700D15D0
		recv	unsigned short	67	0x700D15D2
		fw	unsigned short	0	0x700D15D4
		drop	unsigned short	1	0x700D15D6
		chkerr	unsigned short	0	0x700D15D8
		lenerr	unsigned short	0	0x700D15DA
		memerr	unsigned short	0	0x700D15DC
		rterr	unsigned short	0	0x700D15DE
		proterr	unsigned short	1	0x700D15E0
		opterr	unsigned short	0	0x700D15E2
		err	unsigned short	0	0x700D15E4
		cachehit	unsigned short	0	0x700D15E6
	ip_frag	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D15E8
		xmit	unsigned short	0	0x700D15E8
		recv	unsigned short	0	0x700D15EA
		fw	unsigned short	0	0x700D15EC
		drop	unsigned short	0	0x700D15EE
		chkerr	unsigned short	0	0x700D15F0
		lenerr	unsigned short	0	0x700D15F2
		memerr	unsigned short	0	0x700D15F4
		rterr	unsigned short	0	0x700D15F6
		proterr	unsigned short	0	0x700D15F8
		opterr	unsigned short	0	0x700D15FA
		err	unsigned short	0	0x700D15FC
		cachehit	unsigned short	0	0x700D15FE
	ip	struct stats_proto	{xmit=0,recv=2,fw=0,drop=0,chkerr=0...}	0x700D1600
		xmit	unsigned short	0	0x700D1600
		recv	unsigned short	2	0x700D1602
		fw	unsigned short	0	0x700D1604
		drop	unsigned short	0	0x700D1606
		chkerr	unsigned short	0	0x700D1608
		lenerr	unsigned short	0	0x700D160A
		memerr	unsigned short	0	0x700D160C
		rterr	unsigned short	0	0x700D160E
		proterr	unsigned short	0	0x700D1610
		opterr	unsigned short	0	0x700D1612
		err	unsigned short	0	0x700D1614
		cachehit	unsigned short	0	0x700D1616
	icmp	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D1618
		xmit	unsigned short	0	0x700D1618
		recv	unsigned short	0	0x700D161A
		fw	unsigned short	0	0x700D161C
		drop	unsigned short	0	0x700D161E
		chkerr	unsigned short	0	0x700D1620
		lenerr	unsigned short	0	0x700D1622
		memerr	unsigned short	0	0x700D1624
		rterr	unsigned short	0	0x700D1626
		proterr	unsigned short	0	0x700D1628
		opterr	unsigned short	0	0x700D162A
		err	unsigned short	0	0x700D162C
		cachehit	unsigned short	0	0x700D162E
	igmp	struct stats_igmp	{xmit=0,recv=0,drop=0,chkerr=0,lenerr=0...}	0x700D1630
		xmit	unsigned short	0	0x700D1630
		recv	unsigned short	0	0x700D1632
		drop	unsigned short	0	0x700D1634
		chkerr	unsigned short	0	0x700D1636
		lenerr	unsigned short	0	0x700D1638
		memerr	unsigned short	0	0x700D163A
		proterr	unsigned short	0	0x700D163C
		rx_v1	unsigned short	0	0x700D163E
		rx_group	unsigned short	0	0x700D1640
		rx_general	unsigned short	0	0x700D1642
		rx_report	unsigned short	0	0x700D1644
		tx_join	unsigned short	0	0x700D1646
		tx_leave	unsigned short	0	0x700D1648
		tx_report	unsigned short	0	0x700D164A
	udp	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D164C
		xmit	unsigned short	0	0x700D164C
		recv	unsigned short	0	0x700D164E
		fw	unsigned short	0	0x700D1650
		drop	unsigned short	0	0x700D1652
		chkerr	unsigned short	0	0x700D1654
		lenerr	unsigned short	0	0x700D1656
		memerr	unsigned short	0	0x700D1658
		rterr	unsigned short	0	0x700D165A
		proterr	unsigned short	0	0x700D165C
		opterr	unsigned short	0	0x700D165E
		err	unsigned short	0	0x700D1660
		cachehit	unsigned short	0	0x700D1662
	tcp	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D1664
		xmit	unsigned short	0	0x700D1664
		recv	unsigned short	0	0x700D1666
		fw	unsigned short	0	0x700D1668
		drop	unsigned short	0	0x700D166A
		chkerr	unsigned short	0	0x700D166C
		lenerr	unsigned short	0	0x700D166E
		memerr	unsigned short	0	0x700D1670
		rterr	unsigned short	0	0x700D1672
		proterr	unsigned short	0	0x700D1674
		opterr	unsigned short	0	0x700D1676
		err	unsigned short	0	0x700D1678
		cachehit	unsigned short	0	0x700D167A
	mem	struct stats_mem	{name=0x7012FF48 {77 'M'},err=0,avail=0,used=240,max=240...}	0x700D167C
		name	unsigned char *	0x7012FF48 "MEM	0x700D167C
		err	unsigned short	0	0x700D1680
		avail	unsigned short	0	0x700D1682
		used	unsigned short	240	0x700D1684
		max	unsigned short	240	0x700D1686
		illegal	unsigned short	0	0x700D1688
	memp	struct stats_mem *[22]	[0x700D30F8 {name=0x7012FE94 {82 'R'},err=0,avail=3,used=0,max=0...},0x700D3188 ...,...	0x700D168C
		[0]	struct stats_mem *	0x700D30F8 {name=0x7012FE94 {82 'R'},err=0,avail=3,used=0,max=0...}	0x700D168C
		[1]	struct stats_mem *	0x700D3188 {name=0x7012FE8C {85 'U'},err=0,avail=4,used=2,max=2...}	0x700D1690
		[2]	struct stats_mem *	0x700D3158 {name=0x7012FE6C {84 'T'},err=0,avail=5,used=1,max=2...}	0x700D1694
		[3]	struct stats_mem *	0x700D3168 {name=0x7012F606 {84 'T'},err=0,avail=8,used=2,max=2...}	0x700D1698
		[4]	struct stats_mem *	0x700D3178 {name=0x7012FE74 {84 'T'},err=0,avail=128,used=0,max=0...}	0x700D169C
		[5]	struct stats_mem *	0x700D3038 {name=0x7012FCA3 {65 'A'},err=0,avail=5,used=0,max=0...}	0x700D16A0
		[6]	struct stats_mem *	0x700D3108 {name=0x7012FD89 {82 'R'},err=0,avail=10,used=0,max=0...}	0x700D16A4
		[7]	struct stats_mem *	0x700D3058 {name=0x7012FD07 {70 'F'},err=0,avail=15,used=0,max=0...}	0x700D16A8
		[8]	struct stats_mem *	0x700D3078 {name=0x7012FEE1 {78 'N'},err=0,avail=2,used=0,max=0...}	0x700D16AC
		[9]	struct stats_mem *	0x700D3088 {name=0x7012FE7C {78 'N'},err=0,avail=10,used=3,max=3...}	0x700D16B0
		[10]	struct stats_mem *	0x700D3138 {name=0x7012F7E8 {84 'T'},err=0,avail=128,used=1,max=1...}	0x700D16B4
		[11]	struct stats_mem *	0x700D3148 {name=0x7012F3CA {84 'T'},err=0,avail=128,used=76,max=76...}	0x700D16B8
		[12]	struct stats_mem *	0x700D3048 {name=0x7012FCB7 {65 'A'},err=0,avail=30,used=0,max=0...}	0x700D16BC
		[13]	struct stats_mem *	0x700D3068 {name=0x7012FBE1 {73 'I'},err=0,avail=8,used=0,max=0...}	0x700D16C0
		[14]	struct stats_mem *	0x700D3128 {name=0x7012FB79 {83 'S'},err=0,avail=17,used=7,max=7...}	0x700D16C4
		[15]	struct stats_mem *	0x700D3098 {name=0x7012FF0E {78 'N'},err=0,avail=1,used=0,max=0...}	0x700D16C8
		[16]	struct stats_mem *	0x700D30A8 {name=0x7012F995 {80 'P'},err=0,avail=16,used=0,max=0...}	0x700D16CC
		[17]	struct stats_mem *	0x700D30B8 {name=0x7012FD4D {80 'P'},err=13,avail=64,used=64,max=64...}	0x700D16D0
		[18]	struct stats_mem *	0x700D30C8 {name=0x7012FBC0 {77 'M'},err=0,avail=100,used=3,max=3...}	0x700D16D4
		[19]	struct stats_mem *	0x700D30D8 {name=0x7012FB61 {77 'M'},err=0,avail=48,used=0,max=0...}	0x700D16D8
		[20]	struct stats_mem *	0x700D30E8 {name=0x7012FA95 {77 'M'},err=0,avail=4,used=0,max=0...}	0x700D16DC
		[21]	struct stats_mem *	0x700D3118 {name=0x7012FE1B {83 'S'},err=0,avail=22,used=0,max=0...}	0x700D16E0
	sys	struct stats_sys	{sem={used=3,max=3,err=0},mutex={used=1,max=1,err=0},mbox={used=4,max=4,err=0}}	0x700D16E4
		sem	struct stats_syselem	{used=3,max=3,err=0}	0x700D16E4
			used	unsigned short	3
			max	unsigned short	3
			err	unsigned short	0
		mutex	struct stats_syselem	{used=1,max=1,err=0}	0x700D16EA
			used	unsigned short	1
			max	unsigned short	1
			err	unsigned short	0
		mbox	struct stats_syselem	{used=4,max=4,err=0}	0x700D16F0
			used	unsigned short	4
			max	unsigned short	4
			err	unsigned short	0
	mib2	struct stats_mib2	{ipinhdrerrors=0,ipinaddrerrors=0,ipinunknownprotos=0,ipindiscards=0,ipindelivers=...	0x700D16F8
		ipinhdrerrors	unsigned int	0	0x700D16F8
		ipinaddrerrors	unsigned int	0	0x700D16FC
		ipinunknownprotos	unsigned int	0	0x700D1700
		ipindiscards	unsigned int	0	0x700D1704
		ipindelivers	unsigned int	0	0x700D1708
		ipoutrequests	unsigned int	0	0x700D170C
		ipoutdiscards	unsigned int	0	0x700D1710
		ipoutnoroutes	unsigned int	2	0x700D1714
		ipreasmoks	unsigned int	0	0x700D1718
		ipreasmfails	unsigned int	0	0x700D171C
		ipfragoks	unsigned int	0	0x700D1720
		ipfragfails	unsigned int	0	0x700D1724
		ipfragcreates	unsigned int	0	0x700D1728
		ipreasmreqds	unsigned int	0	0x700D172C
		ipforwdatagrams	unsigned int	0	0x700D1730
		ipinreceives	unsigned int	2	0x700D1734
		tcpactiveopens	unsigned int	0	0x700D1738
		tcppassiveopens	unsigned int	0	0x700D173C
		tcpattemptfails	unsigned int	0	0x700D1740
		tcpestabresets	unsigned int	0	0x700D1744
		tcpoutsegs	unsigned int	0	0x700D1748
		tcpretranssegs	unsigned int	0	0x700D174C
		tcpinsegs	unsigned int	0	0x700D1750
		tcpinerrs	unsigned int	0	0x700D1754
		tcpoutrsts	unsigned int	0	0x700D1758
		udpindatagrams	unsigned int	0	0x700D175C
		udpnoports	unsigned int	0	0x700D1760
		udpinerrors	unsigned int	0	0x700D1764
		udpoutdatagrams	unsigned int	0	0x700D1768
		icmpinmsgs	unsigned int	0	0x700D176C
		icmpinerrors	unsigned int	0	0x700D1770
		icmpindestunreachs	unsigned int	0	0x700D1774
		icmpintimeexcds	unsigned int	0	0x700D1778
		icmpinparmprobs	unsigned int	0	0x700D177C
		icmpinsrcquenchs	unsigned int	0	0x700D1780
		icmpinredirects	unsigned int	0	0x700D1784
		icmpinechos	unsigned int	0	0x700D1788
		icmpinechoreps	unsigned int	0	0x700D178C
		icmpintimestamps	unsigned int	0	0x700D1790
		icmpintimestampreps	unsigned int	0	0x700D1794
		icmpinaddrmasks	unsigned int	0	0x700D1798
		icmpinaddrmaskreps	unsigned int	0	0x700D179C
		icmpoutmsgs	unsigned int	0	0x700D17A0
		icmpouterrors	unsigned int	0	0x700D17A4
		icmpoutdestunreachs	unsigned int	0	0x700D17A8
		icmpouttimeexcds	unsigned int	0	0x700D17AC
		icmpoutechos	unsigned int	0	0x700D17B0
		icmpoutechoreps	unsigned int	0	0x700D17B4

8 months ago

0 Archit Dev 8 months ago

TI__Intellectual 2400 points

Hi TollMan,

I have some points here:

1. Can you first check if the Link ISR is being triggered? Put a breakpoint in the ISR ICSS_EMAC_linkISR and disconnect or connect the cable on the port. The breakpoint should get hit.

2.

TollMan said:
I understand that PING does not work, but I expect that the ARP request from the PC PINGing the Control Card will trigger an ARP Announcement transmission from the Control Card. However, I see no transmissions from Control Card when running ICSS-EMAC.

Here, we need to check if the ping packets are being received by the DUT and being forwarded to the lwIP stack. It is possible to disable Rx in firmware through IOCTL. This is controlled through a location in ICSS memory. Check the memory correspnding to portControlAddr configured in ICSS_EMAC_FwStaticMmap. 0x1 value for this byte means Rx is disabled , and 0x0 means Rx is enabled. Check this as a very first step.

3. As a next step, can you check if Rx interrupt is being asserted?

This can be one of the reasons why Host would not receive packets. Put a break point in ICSS_EMAC_rxInterruptHandler and send a single packet using any PC based tool. The ISR should get hit.

4. As a next step, we need to check if the packet is being sent to the lwIP stack from the ICSS_EMAC driver. Can you put a breakpoint in the "Lwip2Emac_serviceRx" API and check if this breakpoint is being hit?

5.

TollMan said:
I put breakpoints in icss_emac.c at, ICSS_EMAC_txPacketEnqueue(). This revealed that icss_emac transmit is executing.

I put a breakpoint in lwip2icss_emac.c at Lwip2Emac_sendTxPackets(). This breakpoint is not hit.

ICSS_EMAC_txPacket (and subsequently, ICSS_EMAC_txPacketEnqueue) is called internally from the Lwip2Emac_sendTxPackets. Can you check the call stack as to who is calling this ICSS_EMAC_txPacketEnqueue API?

Regards
Archit Dev

0 Archit Dev 8 months ago in reply to Archit Dev

TI__Intellectual 2400 points

Hi TollMan,

Both Nilabh Anand and I are out-of-office this week. So please expect a delay in responses.

Your patience is really appreciated.

Regards
Archit Dev

0 TollMan 8 months ago in reply to Archit Dev

Intellectual 445 points

Hi Archit,

Regarding:

"Can you first check if the Link ISR is being triggered? Put a breakpoint in the ISR ICSS_EMAC_linkISR and disconnect or connect the cable on the port. The breakpoint should get hit."

I tested the link ISR. If I start the application with the Ethernet cable disconnected, the Link ISR does not occur. Upon connecting it a breakpoint in the ISR is hit.

This is a screen capture inside the ISR. I stepped through it to the end.

Here are the valuables at that time:

hostStatPtr	struct ICSS_EMAC_HostStatistics_s *	0x700B5694 {txUcast=0,txBcast=0,txMcast=0,txOctets=0,rxUcast=0...}	0x70132F5C
	*(hostStatPtr)	struct ICSS_EMAC_HostStatistics_s	{txUcast=0,txBcast=0,txMcast=0,txOctets=0,rxUcast=0...}	0x700B5694
		txUcast	unsigned int	0	0x700B5694
		txBcast	unsigned int	0	0x700B5698
		txMcast	unsigned int	0	0x700B569C
		txOctets	unsigned int	0	0x700B56A0
		rxUcast	unsigned int	0	0x700B56A4
		rxBcast	unsigned int	0	0x700B56A8
		rxMcast	unsigned int	0	0x700B56AC
		rxOctets	unsigned int	0	0x700B56B0
		rxUnknownProtocol	unsigned int	0	0x700B56B4
		txDroppedPackets	unsigned int	0	0x700B56B8
		linkBreak	unsigned int	2	0x700B56BC
		txCollisionDroppedPackets	unsigned int	0	0x700B56C0
		txNumCollision	unsigned int	0	0x700B56C4
icssEmacHandle	struct ICSS_EMAC_Config_s *	0x70131D80 {object=0x700B1C40,attrs=0x70131A94 {emacMode=3 '\x03',phyAddr=[0,1],phyToMacInterfaceMode=...}	0x70132F84
	*(icssEmacHandle)	struct ICSS_EMAC_Config_s	{object=0x700B1C40,attrs=0x70131A94 {emacMode=3 '\x03',phyAddr=[0,1],phyToMacInterfaceMode=...}	0x70131D80
		object	void *	0x700B1C40	0x70131D80
		attrs	struct const ICSS_EMAC_Attrs_s *	0x70131A94 {emacMode=3 '\x03',phyAddr=[0,1],phyToMacInterfaceMode=0 '\x00',halfDuplexEnable=...	0x70131D84
intStatusPtr	unsigned int *	0x48020284 {1024}	0x70132F6C
	*(intStatusPtr)	unsigned int	1024	0x48020284
ioctlParams	struct ICSS_EMAC_IoctlCmd	{command=2 '\x02',ioctlVal=0x70132F63}	0x70132F64
	command	unsigned char	2 '\x02'	0x70132F64
	ioctlVal	void *	0x70132F63	0x70132F68
		*(ioctlVal)	unknown	cannot load from non-primitive location
ioctlvalue	unsigned char	0 '\x00'	0x70132F63
linkStatus	unsigned int	0	0x70132F70
linkStatusChange	unsigned char	1 '\x01'	0x70132F4F
pollSource	unsigned int	1	0x70132F80
portStatus	unsigned char	0 '\x00'	0x70132F77
portStatusPtr	unsigned char *	0x48003FA0 {0 '\x00'}	0x70132F78
	*(portStatusPtr)	unsigned char	0 '\x00'	0x48003FA0
pruicssHandle	struct PRUICSS_Config_s *	0x70131D88 {object=0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=...,...},hwAttrs=...	0x70132F48
	*(pruicssHandle)	struct PRUICSS_Config_s	{object=0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=0x00000000,hwiObj=...,...},hwAttrs=...	0x70131D88
		object	struct PRUICSS_Object_s *	0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=0x00000000,hwiObj=...,...}	0x70131D88
			*(object)	struct PRUICSS_Object_s	{pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=0x00000000,hwiObj={rsv=[0,...},waitEnable=...,...}	0x700CEB40
				pruicssVersion	unsigned int	515	0x700CEB40
				pruEvntOutFnMapArray	struct PRUICSS_IrqFunMap_s[10]	[{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...,...	0x700CEB44
					[0]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[1]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[2]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[3]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[4]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[5]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[6]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[7]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[8]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
					[9]	struct PRUICSS_IrqFunMap_s	{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...
		hwAttrs	struct const PRUICSS_HWAttrs *	0x70129C08 {instance=0,baseAddr=1207959552,pru0CtrlRegBase=1208098816,pru1CtrlRegBase=...	0x70131D8C
pruicssHwAttrs	struct const PRUICSS_HWAttrs *	0x70129C08 {instance=0,baseAddr=1207959552,pru0CtrlRegBase=1208098816,pru1CtrlRegBase=...	0x70132F44
	*(pruicssHwAttrs)	struct const PRUICSS_HWAttrs	{instance=0,baseAddr=1207959552,pru0CtrlRegBase=1208098816,pru1CtrlRegBase=1208107008,intcRegBase=...	0x70129C08
		instance	unsigned int	0	0x70129C08
		baseAddr	unsigned int	1207959552	0x70129C0C
		pru0CtrlRegBase	unsigned int	1208098816	0x70129C10
		pru1CtrlRegBase	unsigned int	1208107008	0x70129C14
		intcRegBase	unsigned int	1208090624	0x70129C18
		cfgRegBase	unsigned int	1208115200	0x70129C1C
		uartRegBase	unsigned int	1208123392	0x70129C20
		iep0RegBase	unsigned int	1208147968	0x70129C24
		ecapRegBase	unsigned int	1208156160	0x70129C28
		miiRtCfgRegBase	unsigned int	1208164352	0x70129C2C
		miiGRtCfgRegBase	unsigned int	1208168448	0x70129C30
		miiMdioRegBase	unsigned int	1208165376	0x70129C34
		pru0DramBase	unsigned int	1207959552	0x70129C38
		pru1DramBase	unsigned int	1207967744	0x70129C3C
		pru0IramBase	unsigned int	1208172544	0x70129C40
		pru1IramBase	unsigned int	1208188928	0x70129C44
		sharedDramBase	unsigned int	1208025088	0x70129C48
		pru0DramSize	unsigned int	8192	0x70129C4C
		pru1DramSize	unsigned int	8192	0x70129C50
		pru0IramSize	unsigned int	12288	0x70129C54
		pru1IramSize	unsigned int	12288	0x70129C58
		sharedDramSize	unsigned int	32768	0x70129C5C
pStaticMMap	struct ICSS_EMAC_FwStaticMmap_s *	0x700B5C98 {versionOffset=0,version2Offset=4,featureOffset=8,futureFeatureOffset=...	0x70132F58
retVal	int	-1	0x70132F7C
temp_addr	unsigned int	1207975840	0x70132F54
temp_val	unsigned int	0	0x70132F50

Here is a breakpoint at the end of ICSS_EMAC_rxPktInfo2(()

... and the variables at that point:

int32_t ICSS_EMAC_rxPktInfo2(ICSS_EMAC_Handle icssEmacHandle, ICSS_EMAC_PktInfo *pRxPktInfo)

emacMode	unsigned char	0 '\x00'	0x700B9983
finalPrioQueue	unsigned char	3 '\x03'	0x700B9952
i	unsigned char	4 '\x04'	0x700B9951
icssEmacHandle	struct ICSS_EMAC_Config_s *	0x70131D80 {object=0x700B1C40,attrs=0x70131A94 {emacMode=3 '\x03',phyAddr=[0,1],phyToMacInterfaceMode=...}	0x700B999C
	*(icssEmacHandle)	struct ICSS_EMAC_Config_s	{object=0x700B1C40,attrs=0x70131A94 {emacMode=3 '\x03',phyAddr=[0,1],phyToMacInterfaceMode=...}	0x70131D80
		object	void *	0x700B1C40	0x70131D80
		attrs	struct const ICSS_EMAC_Attrs_s *	0x70131A94 {emacMode=3 '\x03',phyAddr=[0,1],phyToMacInterfaceMode=0 '\x00',halfDuplexEnable=...	0x70131D84
initPrioQueue	unsigned char	0 '\x00'	0x700B9953
packet_found	int	1	0x700B9988
pDynamicMMap	struct ICSS_EMAC_FwDynamicMmap_s *	0x700B5CF0 {queueSizeOffset=7728,queueOffset=7704,queueDescriptorOffset=7680,txQueueSize=...	0x700B995C
	*(pDynamicMMap)	struct ICSS_EMAC_FwDynamicMmap_s	{queueSizeOffset=7728,queueOffset=7704,queueDescriptorOffset=7680,txQueueSize=[97,...,rxHostQueueSize=...	0x700B5CF0
		queueSizeOffset	unsigned int	7728	0x700B5CF0
		queueOffset	unsigned int	7704	0x700B5CF4
		queueDescriptorOffset	unsigned int	7680	0x700B5CF8
		txQueueSize	unsigned int[16]	[97,97,97,97,0...]	0x700B5CFC
		rxHostQueueSize	unsigned int[16]	[194,194,194,194,0...]	0x700B5D3C
		collisionQueueSize	unsigned int	48	0x700B5D7C
		p0Q1BufferDescOffset	unsigned int	1024	0x700B5D80
		p0ColBufferDescOffset	unsigned int	7232	0x700B5D84
		p0Q1BufferOffset	unsigned int	0	0x700B5D88
		transmitQueuesBufferOffset	unsigned int	0	0x700B5D8C
		p0ColBufferOffset	unsigned int	60928	0x700B5D90
		hostQ1RxContextOffset	unsigned int	7240	0x700B5D94
		p1Q1SwitchTxContextOffset	unsigned int	7424	0x700B5D98
		portQueueDescOffset	unsigned int	7872	0x700B5D9C
		q1EmacTxContextOffset	unsigned int	7904	0x700B5DA0
		numQueues	unsigned int	4	0x700B5DA4
pruicssHandle	struct PRUICSS_Config_s *	0x70131D88 {object=0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=...,...},hwAttrs=...	0x700B9958
	*(pruicssHandle)	struct PRUICSS_Config_s	{object=0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=0x00000000,hwiObj=...,...},hwAttrs=...	0x70131D88
		object	struct PRUICSS_Object_s *	0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=0x00000000,hwiObj=...,...}	0x70131D88
		hwAttrs	struct const PRUICSS_HWAttrs *	0x70129C08 {instance=0,baseAddr=1207959552,pru0CtrlRegBase=1208098816,pru1CtrlRegBase=...	0x70131D8C
pruicssHwAttrs	struct const PRUICSS_HWAttrs *	0x70129C08 {instance=0,baseAddr=1207959552,pru0CtrlRegBase=1208098816,pru1CtrlRegBase=...	0x700B9954
pRxPktInfo	struct ICSS_EMAC_PktInfo_s *	0x700B99AC {portNumber=1,queueNumber=3,rdBufferL3Addr=1879066816,fdbLookupSuccess=...	0x700B9998
	*(pRxPktInfo)	struct ICSS_EMAC_PktInfo_s	{portNumber=1,queueNumber=3,rdBufferL3Addr=1879066816,fdbLookupSuccess=2779096485,flooded=...	0x700B99AC
		portNumber	unsigned int	1	0x700B99AC
		queueNumber	unsigned int	3	0x700B99B0
		rdBufferL3Addr	unsigned int	1879066816	0x700B99B4
		fdbLookupSuccess	unsigned int	2779096485	0x700B99B8
		flooded	unsigned int	2779096485	0x700B99BC
pStaticMMap	struct ICSS_EMAC_FwStaticMmap_s *	0x700B5C98 {versionOffset=0,version2Offset=4,featureOffset=8,futureFeatureOffset=...	0x700B9960
qDesc	struct ICSS_EMAC_Queue_s *	0x48003E94 {rd_ptr=3352,wr_ptr=4120,busy_s=0 '\x00',status=4 '\x04',max_fill_level=...	0x700B9984
	*(qDesc)	struct ICSS_EMAC_Queue_s	{rd_ptr=3352,wr_ptr=4120,busy_s=0 '\x00',status=4 '\x04',max_fill_level=192 '\xc0'...	0x48003E94
queue_rd_ptr	unsigned short	3352	0x700B9996
queue_wr_ptr	unsigned short	4120	0x700B9994
rd_buf_desc	unsigned int	15794176	0x700B9990
rd_buf_desc_num	unsigned short	0	0x700B996E
rd_buffer_l3_addr	unsigned int	1879066816	0x700B9970
rd_packet_length	unsigned short	60	0x700B998E
rxQueue	struct ICSS_EMAC_QueueParams_s *	0x700B5980 {qStat={rawCount=0,errCount=86},buffer_offset=18624,buffer_desc_offset=...	0x700B9968
shadow	unsigned short	0	0x700B9976
sPort	struct ICSS_EMAC_PortParams_s *	0x700B5944 {ptcpPktBuff=0x00000000 {24 '\x18'},rawCount=0,errCount=0,queue=[{qStat=...,...}	0x700B9964
temp_addr	unsigned int	1	0x700B997C
temp_var1	unsigned int	24	0x700B9978

I do not see any obvious problem here.

Regarding:

"Can you check the call stack as to who is calling this ICSS_EMAC_txPacketEnqueue API?"

Since a breakpoint in ICSS_EMAC_txPacketEnqueue() never gets hit (that code is not executing) I cannot check the call stack.

It looks to me that, although the ICSS_EMAC is receiving the ARP request from the PC, like the ARP Announcement (transmission) from the Control Card is not happening for some reason.

Please advise.

Regards,

Tollman

0 Prajith Jayarajan 7 months ago in reply to TollMan

TI__Expert 7325 points

Hi Tollman,

Archit is out of office today, please expect a reply by tomorrow.

From the statistics it looks like the lwip is receiving the packet (from recv stat), but not sending anything back (from xmt stat). One possibility I can think of is buffer corruption. Could you check if ARPs are transmitted to lwip stack properly

Regards,
Prajith

0 TollMan 7 months ago in reply to Prajith Jayarajan

Intellectual 445 points

Hi Prajith:

I captured the ARP Announcement (transmission) from the Control Card in ICSS_EMAC_txPacketEnqueue().

Note I am still seeing what appear to be packet allocation errors, although I cannot definitively conclude that these errors are the root cause to the dropped ARP transmissions.

[Cortex_R5_0] MII mode
load to PRU0 passed
load to PRU1 passed
Starting lwIP, local interface IP is 192.168.2.252
[LWIPIF_LWIP]Link is Up on port 1
[LWIPIF_LWIP] Interface layer handle is Initialised
[LWIPIF_LWIP] NETIF INIT SUCCESS
status_callback==UP, local interface IP is 192.168.2.252
UDP server listening on port 5001
link_callback==UP
[LWIPIF_LWIP]ERROR: Rx Pbuf_alloc() in LWIPIF_LWIP_INPUT failure.!
[LWIPIF_LWIP]ERROR: Rx Pbuf_alloc() in LWIPIF_LWIP_INPUT failure.!
[LWIPIF_LWIP]ERROR: Rx Pbuf_alloc() in LWIPIF_LWIP_INPUT failure.!
[LWIPIF_LWIP]ERROR: Rx Pbuf_alloc() in LWIPIF_LWIP_INPUT failure.!
[LWIPIF_LWIP]ERROR: Rx Pbuf_alloc() in LWIPIF_LWIP_INPUT failure.!
[LWIPIF_LWIP]ERROR: Rx Pbuf_alloc() in LWIPIF_LWIP_INPUT failure.!

This is a view of CCS at the time.

These are the variable at that time:

int32_t ICSS_EMAC_txPacketEnqueue()

buffer_des	unsigned int	15728640	0x700D5608
buffer_offset_computed	unsigned int	34528	0x700D560C
col_queue_already_occupied	unsigned short	0	0x700D55EC
collision_queue_selected	unsigned int	0	0x700D55F0
collision_status	unsigned short	0	0x700D55EE
emacMode	unsigned char	0 '\x00'	0x700D55D2
hostStatPtr	struct ICSS_EMAC_HostStatistics_s *	0x700B5694 {txUcast=6,txBcast=0,txMcast=0,txOctets=384,rxUcast=0...}	0x700D55D4
	*(hostStatPtr)	struct ICSS_EMAC_HostStatistics_s	{txUcast=6,txBcast=0,txMcast=0,txOctets=384,rxUcast=0...}	0x700B5694
		txUcast	unsigned int	6	0x700B5694
		txBcast	unsigned int	0	0x700B5698
		txMcast	unsigned int	0	0x700B569C
		txOctets	unsigned int	384	0x700B56A0
		rxUcast	unsigned int	0	0x700B56A4
		rxBcast	unsigned int	7	0x700B56A8
		rxMcast	unsigned int	10	0x700B56AC
		rxOctets	unsigned int	2566	0x700B56B0
		rxUnknownProtocol	unsigned int	2	0x700B56B4
		txDroppedPackets	unsigned int	0	0x700B56B8
		linkBreak	unsigned int	2	0x700B56BC
		txCollisionDroppedPackets	unsigned int	0	0x700B56C0
		txNumCollision	unsigned int	0	0x700B56C4
i	unsigned short	18	0x700D55F6
icssEmacHandle	struct ICSS_EMAC_Config_s *	0x70131D80 {object=0x700B1C40,attrs=0x70131A94 {emacMode=3 '\x03',phyAddr=[0,1],phyToMacInterfaceMode=...}	0x700D5618
lengthOfPacket	unsigned short	60	0x700D5610
linkStatus	unsigned char	1 '\x01'	0x700D55D3
macAddr	unsigned char *	0x700C7DF2 {0 '\x00'}	0x700D55E0
new_packet_length	unsigned short	0	0x700D55FC
num_of_bytes	unsigned short	0	0x700D55FE
original_length_of_packet	unsigned short	42	0x700D55EA
packet_min_size_padding	unsigned short	1	0x700D55E8
pDynamicMMap	struct ICSS_EMAC_FwDynamicMmap_s *	0x700B5CF0 {queueSizeOffset=7728,queueOffset=7704,queueDescriptorOffset=7680,txQueueSize=...	0x700D55C8
	*(pDynamicMMap)	struct ICSS_EMAC_FwDynamicMmap_s	{queueSizeOffset=7728,queueOffset=7704,queueDescriptorOffset=7680,txQueueSize=[97,...,rxHostQueueSize=...	0x700B5CF0
		queueSizeOffset	unsigned int	7728	0x700B5CF0
		queueOffset	unsigned int	7704	0x700B5CF4
		queueDescriptorOffset	unsigned int	7680	0x700B5CF8
		txQueueSize	unsigned int[16]	[97,97,97,97,0...]	0x700B5CFC
			[0]	unsigned int	97	0x700B5CFC
			[1]	unsigned int	97	0x700B5D00
			[2]	unsigned int	97	0x700B5D04
			[3]	unsigned int	97	0x700B5D08
			[4]	unsigned int	0	0x700B5D0C
			[5]	unsigned int	0	0x700B5D10
			[6]	unsigned int	0	0x700B5D14
			[7]	unsigned int	0	0x700B5D18
			[8]	unsigned int	0	0x700B5D1C
			[9]	unsigned int	0	0x700B5D20
			[10]	unsigned int	0	0x700B5D24
			[11]	unsigned int	0	0x700B5D28
			[12]	unsigned int	0	0x700B5D2C
			[13]	unsigned int	0	0x700B5D30
			[14]	unsigned int	0	0x700B5D34
			[15]	unsigned int	0	0x700B5D38
		rxHostQueueSize	unsigned int[16]	[194,194,194,194,0...]	0x700B5D3C
			[0]	unsigned int	194	0x700B5D3C
			[1]	unsigned int	194	0x700B5D40
			[2]	unsigned int	194	0x700B5D44
			[3]	unsigned int	194	0x700B5D48
			[4]	unsigned int	0	0x700B5D4C
			[5]	unsigned int	0	0x700B5D50
			[6]	unsigned int	0	0x700B5D54
			[7]	unsigned int	0	0x700B5D58
			[8]	unsigned int	0	0x700B5D5C
			[9]	unsigned int	0	0x700B5D60
			[10]	unsigned int	0	0x700B5D64
			[11]	unsigned int	0	0x700B5D68
			[12]	unsigned int	0	0x700B5D6C
			[13]	unsigned int	0	0x700B5D70
			[14]	unsigned int	0	0x700B5D74
			[15]	unsigned int	0	0x700B5D78
		collisionQueueSize	unsigned int	48	0x700B5D7C
		p0Q1BufferDescOffset	unsigned int	1024	0x700B5D80
		p0ColBufferDescOffset	unsigned int	7232	0x700B5D84
		p0Q1BufferOffset	unsigned int	0	0x700B5D88
		transmitQueuesBufferOffset	unsigned int	0	0x700B5D8C
		p0ColBufferOffset	unsigned int	60928	0x700B5D90
		hostQ1RxContextOffset	unsigned int	7240	0x700B5D94
		p1Q1SwitchTxContextOffset	unsigned int	7424	0x700B5D98
		portQueueDescOffset	unsigned int	7872	0x700B5D9C
		q1EmacTxContextOffset	unsigned int	7904	0x700B5DA0
		numQueues	unsigned int	4	0x700B5DA4
portNumber	unsigned char	1 '\x01'	0x700D5613
pruicssHandle	struct PRUICSS_Config_s *	0x70131D88 {object=0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=...,...},hwAttrs=...	0x700D55C0
	*(pruicssHandle)	struct PRUICSS_Config_s	{object=0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=0x00000000,hwiObj=...,...},hwAttrs=...	0x70131D88
		object	struct PRUICSS_Object_s *	0x700CEB40 {pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=0x00000000,hwiObj=...,...}	0x70131D88
			*(object)	struct PRUICSS_Object_s	{pruicssVersion=515,pruEvntOutFnMapArray=[{irqHandler=0x00000000,hwiObj={rsv=[0,...},waitEnable=...,...}	0x700CEB40
				pruicssVersion	unsigned int	515
				pruEvntOutFnMapArray	struct PRUICSS_IrqFunMap_s[10]	[{irqHandler=0x00000000,hwiObj={rsv=[0,0,0,0,0...]},waitEnable=0 '\x00',semObj={rsv=...,pruicssHandle=...,...
					[0]	struct PRUICSS_IrqFunMap_s
						irqHandler
						hwiObj









						waitEnable
						semObj
						pruicssHandle
					[1]	struct PRUICSS_IrqFunMap_s
						irqHandler
						hwiObj









						waitEnable
						semObj
						pruicssHandle
					[2]	struct PRUICSS_IrqFunMap_s
					[3]	struct PRUICSS_IrqFunMap_s
					[4]	struct PRUICSS_IrqFunMap_s
					[5]	struct PRUICSS_IrqFunMap_s
					[6]	struct PRUICSS_IrqFunMap_s
					[7]	struct PRUICSS_IrqFunMap_s
					[8]	struct PRUICSS_IrqFunMap_s
					[9]	struct PRUICSS_IrqFunMap_s
		hwAttrs	struct const PRUICSS_HWAttrs *	0x70129C08 {instance=0,baseAddr=1207959552,pru0CtrlRegBase=1208098816,pru1CtrlRegBase=...	0x70131D8C
pruicssHwAttrs	struct const PRUICSS_HWAttrs *	0x70129C08 {instance=0,baseAddr=1207959552,pru0CtrlRegBase=1208098816,pru1CtrlRegBase=...	0x700D55BC
	*(pruicssHwAttrs)	struct const PRUICSS_HWAttrs	{instance=0x00000000,baseAddr=0x48000000,pru0CtrlRegBase=0x48022000,pru1CtrlRegBase=... (Hex)	0x70129C08
		instance	unsigned int	0x00000000 (Hex)	0x70129C08
		baseAddr	unsigned int	0x48000000 (Hex)	0x70129C0C
		pru0CtrlRegBase	unsigned int	0x48022000 (Hex)	0x70129C10
		pru1CtrlRegBase	unsigned int	0x48024000 (Hex)	0x70129C14
		intcRegBase	unsigned int	0x48020000 (Hex)	0x70129C18
		cfgRegBase	unsigned int	0x48026000 (Hex)	0x70129C1C
		uartRegBase	unsigned int	0x48028000 (Hex)	0x70129C20
		iep0RegBase	unsigned int	0x4802E000 (Hex)	0x70129C24
		ecapRegBase	unsigned int	0x48030000 (Hex)	0x70129C28
		miiRtCfgRegBase	unsigned int	0x48032000 (Hex)	0x70129C2C
		miiGRtCfgRegBase	unsigned int	0x48033000 (Hex)	0x70129C30
		miiMdioRegBase	unsigned int	0x48032400 (Hex)	0x70129C34
		pru0DramBase	unsigned int	0x48000000 (Hex)	0x70129C38
		pru1DramBase	unsigned int	0x48002000 (Hex)	0x70129C3C
		pru0IramBase	unsigned int	0x48034000 (Hex)	0x70129C40
		pru1IramBase	unsigned int	0x48038000 (Hex)	0x70129C44
		sharedDramBase	unsigned int	0x48010000 (Hex)	0x70129C48
		pru0DramSize	unsigned int	0x00002000 (Hex)	0x70129C4C
		pru1DramSize	unsigned int	0x00002000 (Hex)	0x70129C50
		pru0IramSize	unsigned int	0x00003000 (Hex)	0x70129C54
		pru1IramSize	unsigned int	0x00003000 (Hex)	0x70129C58
		sharedDramSize	unsigned int	0x00008000 (Hex)	0x70129C5C
pruSharedMem	unsigned int	0	0x700D55DC
pStaticMMap	struct ICSS_EMAC_FwStaticMmap_s *	0x700B5C98 {versionOffset=0,version2Offset=4,featureOffset=8,futureFeatureOffset=...	0x700D55C4
	*(pStaticMMap)	struct ICSS_EMAC_FwStaticMmap_s	{versionOffset=0,version2Offset=4,featureOffset=8,futureFeatureOffset=12,statisticsOffset=...	0x700B5C98
		versionOffset	unsigned int	0	0x700B5C98
		version2Offset	unsigned int	4	0x700B5C9C
		featureOffset	unsigned int	8	0x700B5CA0
		futureFeatureOffset	unsigned int	12	0x700B5CA4
		statisticsOffset	unsigned int	7936	0x700B5CA8
		statisticsSize	unsigned int	152	0x700B5CAC
		stormPreventionOffsetBC	unsigned int	8088	0x700B5CB0
		phySpeedOffset	unsigned int	8092	0x700B5CB4
		portStatusOffset	unsigned int	8096	0x700B5CB8
		portControlAddr	unsigned int	8102	0x700B5CBC
		portMacAddr	unsigned int	8106	0x700B5CC0
		rxInterruptStatusOffset	unsigned int	8112	0x700B5CC4
		stormPreventionOffsetMC	unsigned int	8113	0x700B5CC8
		stormPreventionOffsetUC	unsigned int	8117	0x700B5CCC
		p0QueueDescOffset	unsigned int	7804	0x700B5CD0
		p0ColQueueDescOffset	unsigned int	7780	0x700B5CD4
		emacTtsConfigBaseOffset	unsigned int	7832	0x700B5CD8
		interfaceMacAddrOffset	unsigned int	7768	0x700B5CDC
		colStatusAddr	unsigned int	7776	0x700B5CE0
		promiscuousModeOffset	unsigned int	7236	0x700B5CE4
		specialUnicastMACAddrOffset	unsigned int	0	0x700B5CE8
		specialUnicastMACAddressFeatureEnableOffset	unsigned int	0	0x700B5CEC
queue_rd_ptr	unsigned short	5300	0x700D5600
queue_wr_ptr	unsigned short	5340	0x700D5606
queuePriority	unsigned char	3 '\x03'	0x700D5612
remaining_valid_frame_data_length	unsigned short	0	0x700D55E6
size	unsigned short	5680	0x700D5602
sPort	struct ICSS_EMAC_PortParams_s *	0x700B5A60 {ptcpPktBuff=0x00000000 {24 '\x18'},rawCount=0,errCount=0,queue=[{qStat=...,...}	0x700D55B8
	*(sPort)	struct ICSS_EMAC_PortParams_s	{ptcpPktBuff=0x00000000 {24 '\x18'},rawCount=0,errCount=0,queue=[{qStat={rawCount=...,buffer_offset=...,...}	0x700B5A60
		ptcpPktBuff	unsigned char *	0x00000000 "\030\360\237\345\030\360\237\345\030\360..."	0x700B5A60
		rawCount	unsigned int	0	0x700B5A64
		errCount	unsigned int	0	0x700B5A68
		queue	struct ICSS_EMAC_QueueParams_s[17]	[{qStat={rawCount=0,errCount=0},buffer_offset=24832,buffer_desc_offset=4128,queue_desc_offset=...,...	0x700B5A6C
			[0]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=24832,buffer_desc_offset=4128,queue_desc_offset=...	0x700B5A6C
				qStat	struct ICSS_EMAC_QueueStats	{rawCount=0,errCount=0}
				buffer_offset	unsigned short	24832
				buffer_desc_offset	unsigned short	4128
				queue_desc_offset	unsigned short	7836
				queue_size	unsigned short	4516
			[1]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=27936,buffer_desc_offset=4516,queue_desc_offset=...	0x700B5A7C
				qStat	struct ICSS_EMAC_QueueStats	{rawCount=0,errCount=0}
					rawCount	unsigned int
					errCount	unsigned int
				buffer_offset	unsigned short	27936
				buffer_desc_offset	unsigned short	4516
				queue_desc_offset	unsigned short	7844
				queue_size	unsigned short	4904
			[2]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=31040,buffer_desc_offset=4904,queue_desc_offset=...	0x700B5A8C
			[3]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=6,errCount=0},buffer_offset=34144,buffer_desc_offset=5292,queue_desc_offset=...	0x700B5A9C
			[4]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5AAC
			[5]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5ABC
			[6]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5ACC
			[7]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5ADC
			[8]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5AEC
			[9]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5AFC
			[10]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5B0C
			[11]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5B1C
			[12]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5B2C
			[13]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5B3C
			[14]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5B4C
			[15]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=0,buffer_desc_offset=0,queue_desc_offset=...	0x700B5B5C
			[16]	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=0,errCount=0},buffer_offset=62464,buffer_desc_offset=7424,queue_desc_offset=...	0x700B5B6C
srcAddress	unsigned char *	0x700C7DF2 {0 '\x00'}	0x700D5614
temp	unsigned int	349967540	0x700D55F8
temp_addr	unsigned int	1207975606	0x700D55CC
temp_var	unsigned short	34528	0x700D55D0
txQueue	struct ICSS_EMAC_QueueParams_s *	0x700B5A9C {qStat={rawCount=6,errCount=0},buffer_offset=34144,buffer_desc_offset=...	0x700D55D8
	*(txQueue)	struct ICSS_EMAC_QueueParams_s	{qStat={rawCount=6,errCount=0},buffer_offset=34144,buffer_desc_offset=5292,queue_desc_offset=...	0x700B5A9C
		qStat	struct ICSS_EMAC_QueueStats	{rawCount=6,errCount=0}	0x700B5A9C
			rawCount	unsigned int	6	0x700B5A9C
			errCount	unsigned int	0	0x700B5AA0
		buffer_offset	unsigned short	34144	0x700B5AA4
		buffer_desc_offset	unsigned short	5292	0x700B5AA6
		queue_desc_offset	unsigned short	7860	0x700B5AA8
		queue_size	unsigned short	5680	0x700B5AAA
wrk_queue_wr_ptr	unsigned short	5348	0x700D5604

These are the LwIP stats at that time.

int32_t ICSS_EMAC_txPacketEnqueue()

lwip_stats	struct stats_	{link={xmit=0,recv=0,fw=0,drop=0,chkerr=0...},etharp={xmit=6,recv=7,fw=0,drop=2,chkerr=...,ip_frag=...	0x700D15B8
	link	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D15B8
	etharp	struct stats_proto	{xmit=6,recv=7,fw=0,drop=2,chkerr=0...}	0x700D15D0
		xmit	unsigned short	6	0x700D15D0
		recv	unsigned short	7	0x700D15D2
		fw	unsigned short	0	0x700D15D4
		drop	unsigned short	2	0x700D15D6
		chkerr	unsigned short	0	0x700D15D8
		lenerr	unsigned short	0	0x700D15DA
		memerr	unsigned short	0	0x700D15DC
		rterr	unsigned short	0	0x700D15DE
		proterr	unsigned short	2	0x700D15E0
		opterr	unsigned short	0	0x700D15E2
		err	unsigned short	0	0x700D15E4
		cachehit	unsigned short	0	0x700D15E6
	ip_frag	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D15E8
		xmit	unsigned short	0	0x700D15E8
		recv	unsigned short	0	0x700D15EA
		fw	unsigned short	0	0x700D15EC
		drop	unsigned short	0	0x700D15EE
		chkerr	unsigned short	0	0x700D15F0
		lenerr	unsigned short	0	0x700D15F2
		memerr	unsigned short	0	0x700D15F4
		rterr	unsigned short	0	0x700D15F6
		proterr	unsigned short	0	0x700D15F8
		opterr	unsigned short	0	0x700D15FA
		err	unsigned short	0	0x700D15FC
		cachehit	unsigned short	0	0x700D15FE
	ip	struct stats_proto	{xmit=0,recv=8,fw=0,drop=0,chkerr=0...}	0x700D1600
		xmit	unsigned short	0	0x700D1600
		recv	unsigned short	8	0x700D1602
		fw	unsigned short	0	0x700D1604
		drop	unsigned short	0	0x700D1606
		chkerr	unsigned short	0	0x700D1608
		lenerr	unsigned short	0	0x700D160A
		memerr	unsigned short	0	0x700D160C
		rterr	unsigned short	0	0x700D160E
		proterr	unsigned short	0	0x700D1610
		opterr	unsigned short	0	0x700D1612
		err	unsigned short	0	0x700D1614
		cachehit	unsigned short	0	0x700D1616
	icmp	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D1618
		xmit	unsigned short	0	0x700D1618
		recv	unsigned short	0	0x700D161A
		fw	unsigned short	0	0x700D161C
		drop	unsigned short	0	0x700D161E
		chkerr	unsigned short	0	0x700D1620
		lenerr	unsigned short	0	0x700D1622
		memerr	unsigned short	0	0x700D1624
		rterr	unsigned short	0	0x700D1626
		proterr	unsigned short	0	0x700D1628
		opterr	unsigned short	0	0x700D162A
		err	unsigned short	0	0x700D162C
		cachehit	unsigned short	0	0x700D162E
	igmp	struct stats_igmp	{xmit=0,recv=0,drop=0,chkerr=0,lenerr=0...}	0x700D1630
		xmit	unsigned short	0	0x700D1630
		recv	unsigned short	0	0x700D1632
		drop	unsigned short	0	0x700D1634
		chkerr	unsigned short	0	0x700D1636
		lenerr	unsigned short	0	0x700D1638
		memerr	unsigned short	0	0x700D163A
		proterr	unsigned short	0	0x700D163C
		rx_v1	unsigned short	0	0x700D163E
		rx_group	unsigned short	0	0x700D1640
		rx_general	unsigned short	0	0x700D1642
		rx_report	unsigned short	0	0x700D1644
		tx_join	unsigned short	0	0x700D1646
		tx_leave	unsigned short	0	0x700D1648
		tx_report	unsigned short	0	0x700D164A
	udp	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D164C
		xmit	unsigned short	0	0x700D164C
		recv	unsigned short	0	0x700D164E
		fw	unsigned short	0	0x700D1650
		drop	unsigned short	0	0x700D1652
		chkerr	unsigned short	0	0x700D1654
		lenerr	unsigned short	0	0x700D1656
		memerr	unsigned short	0	0x700D1658
		rterr	unsigned short	0	0x700D165A
		proterr	unsigned short	0	0x700D165C
		opterr	unsigned short	0	0x700D165E
		err	unsigned short	0	0x700D1660
		cachehit	unsigned short	0	0x700D1662
	tcp	struct stats_proto	{xmit=0,recv=0,fw=0,drop=0,chkerr=0...}	0x700D1664
		xmit	unsigned short	0	0x700D1664
		recv	unsigned short	0	0x700D1666
		fw	unsigned short	0	0x700D1668
		drop	unsigned short	0	0x700D166A
		chkerr	unsigned short	0	0x700D166C
		lenerr	unsigned short	0	0x700D166E
		memerr	unsigned short	0	0x700D1670
		rterr	unsigned short	0	0x700D1672
		proterr	unsigned short	0	0x700D1674
		opterr	unsigned short	0	0x700D1676
		err	unsigned short	0	0x700D1678
		cachehit	unsigned short	0	0x700D167A
	mem	struct stats_mem	{name=0x7012FF48 {77 'M'},err=0,avail=0,used=240,max=240...}	0x700D167C
		name	unsigned char *	0x7012FF48 "MEM	0x700D167C
		err	unsigned short	0	0x700D1680
		avail	unsigned short	0	0x700D1682
		used	unsigned short	240	0x700D1684
		max	unsigned short	240	0x700D1686
		illegal	unsigned short	0	0x700D1688
	memp	struct stats_mem *[22]	[0x700D30F8 {name=0x7012FE94 {82 'R'},err=0,avail=3,used=0,max=0...},0x700D3188 ...,...	0x700D168C
		[0]	struct stats_mem *	0x700D30F8 {name=0x7012FE94 {82 'R'},err=0,avail=3,used=0,max=0...}	0x700D168C
		[1]	struct stats_mem *	0x700D3188 {name=0x7012FE8C {85 'U'},err=0,avail=4,used=2,max=2...}	0x700D1690
		[2]	struct stats_mem *	0x700D3158 {name=0x7012FE6C {84 'T'},err=0,avail=5,used=1,max=2...}	0x700D1694
		[3]	struct stats_mem *	0x700D3168 {name=0x7012F606 {84 'T'},err=0,avail=8,used=2,max=2...}	0x700D1698
		[4]	struct stats_mem *	0x700D3178 {name=0x7012FE74 {84 'T'},err=0,avail=128,used=0,max=0...}	0x700D169C
		[5]	struct stats_mem *	0x700D3038 {name=0x7012FCA3 {65 'A'},err=0,avail=5,used=0,max=0...}	0x700D16A0
		[6]	struct stats_mem *	0x700D3108 {name=0x7012FD89 {82 'R'},err=0,avail=10,used=0,max=0...}	0x700D16A4
		[7]	struct stats_mem *	0x700D3058 {name=0x7012FD07 {70 'F'},err=0,avail=15,used=0,max=0...}	0x700D16A8
		[8]	struct stats_mem *	0x700D3078 {name=0x7012FEE1 {78 'N'},err=0,avail=2,used=0,max=0...}	0x700D16AC
		[9]	struct stats_mem *	0x700D3088 {name=0x7012FE7C {78 'N'},err=0,avail=10,used=3,max=3...}	0x700D16B0
		[10]	struct stats_mem *	0x700D3138 {name=0x7012F7E8 {84 'T'},err=0,avail=128,used=0,max=0...}	0x700D16B4
		[11]	struct stats_mem *	0x700D3148 {name=0x7012F3CA {84 'T'},err=0,avail=128,used=1,max=4...}	0x700D16B8
		[12]	struct stats_mem *	0x700D3048 {name=0x7012FCB7 {65 'A'},err=0,avail=30,used=0,max=0...}	0x700D16BC
		[13]	struct stats_mem *	0x700D3068 {name=0x7012FBE1 {73 'I'},err=0,avail=8,used=0,max=0...}	0x700D16C0
		[14]	struct stats_mem *	0x700D3128 {name=0x7012FB79 {83 'S'},err=0,avail=17,used=7,max=7...}	0x700D16C4
		[15]	struct stats_mem *	0x700D3098 {name=0x7012FF0E {78 'N'},err=0,avail=1,used=0,max=0...}	0x700D16C8
		[16]	struct stats_mem *	0x700D30A8 {name=0x7012F995 {80 'P'},err=0,avail=16,used=0,max=0...}	0x700D16CC
		[17]	struct stats_mem *	0x700D30B8 {name=0x7012FD4D {80 'P'},err=0,avail=64,used=2,max=5...}	0x700D16D0
		[18]	struct stats_mem *	0x700D30C8 {name=0x7012FBC0 {77 'M'},err=0,avail=100,used=3,max=3...}	0x700D16D4
		[19]	struct stats_mem *	0x700D30D8 {name=0x7012FB61 {77 'M'},err=0,avail=48,used=0,max=0...}	0x700D16D8
		[20]	struct stats_mem *	0x700D30E8 {name=0x7012FA95 {77 'M'},err=0,avail=4,used=0,max=0...}	0x700D16DC
		[21]	struct stats_mem *	0x700D3118 {name=0x7012FE1B {83 'S'},err=0,avail=22,used=0,max=0...}	0x700D16E0
	sys	struct stats_sys	{sem={used=3,max=3,err=0},mutex={used=1,max=1,err=0},mbox={used=4,max=4,err=0}}	0x700D16E4
		sem	struct stats_syselem	{used=3,max=3,err=0}	0x700D16E4
		mutex	struct stats_syselem	{used=1,max=1,err=0}	0x700D16EA
		mbox	struct stats_syselem	{used=4,max=4,err=0}	0x700D16F0
	mib2	struct stats_mib2	{ipinhdrerrors=0,ipinaddrerrors=0,ipinunknownprotos=0,ipindiscards=0,ipindelivers=...	0x700D16F8
gI2cConfig	struct I2C_Config_s[2]	[{object=0x700CF72C {mutex={rsv=[0,1879897900,0,0,0...]},transferComplete={rsv=[...},hwiObj=...,hwAttrs=...,...	0x70131D20
	[0]	struct I2C_Config_s	{object=0x700CF72C {mutex={rsv=[0,1879897900,0,0,0...]},transferComplete={rsv=[1879898052,...},hwiObj=...,hwAttrs=...	0x70131D20
		object	struct I2C_Object_s *	0x700CF72C {mutex={rsv=[0,1879897900,0,0,0...]},transferComplete={rsv=[1879898052,...},hwiObj=...	0x70131D20
		hwAttrs	struct const I2C_HwAttrs_s *	0x70131B08 {baseAddr=1380974592,intNum=44,eventId=0,funcClk=96000000,enableIntr=...	0x70131D24
	[1]	struct I2C_Config_s	{object=0x700CF940 {mutex={rsv=[0,1879898432,0,0,0...]},transferComplete={rsv=[1879898584,...},hwiObj=...,hwAttrs=...	0x70131D28
gMpuRegionConfig	struct MpuP_RegionConfig_[7]	[{baseAddr=0,size=30,attrs={isEnable=1 '\x01',isCacheable=0 '\x00',isBufferable=...},...	0x7012890C
	[0]	struct MpuP_RegionConfig_	{baseAddr=0,size=30,attrs={isEnable=1 '\x01',isCacheable=0 '\x00',isBufferable=0 '\x00',isSharable=...}	0x7012890C
		baseAddr	unsigned int	0	0x7012890C
		size	unsigned int	30	0x70128910
		attrs	struct MpuP_RegionAttrs	{isEnable=1 '\x01',isCacheable=0 '\x00',isBufferable=0 '\x00',isSharable=1 '\x01',isExecuteNever=...	0x70128914
			isEnable	unsigned char	1 '\x01'	0x70128914
			isCacheable	unsigned char	0 '\x00'	0x70128915
			isBufferable	unsigned char	0 '\x00'	0x70128916
			isSharable	unsigned char	1 '\x01'	0x70128917
			isExecuteNever	unsigned char	1 '\x01'	0x70128918
			tex	unsigned char	0 '\x00'	0x70128919
			accessPerm	unsigned char	2 '\x02'	0x7012891A
			subregionDisableMask	unsigned char	0 '\x00'	0x7012891B
	[1]	struct MpuP_RegionConfig_	{baseAddr=0,size=14,attrs={isEnable=1 '\x01',isCacheable=1 '\x01',isBufferable=1 '\x01',isSharable=...}	0x7012891C
		baseAddr	unsigned int	0	0x7012891C
		size	unsigned int	14	0x70128920
		attrs	struct MpuP_RegionAttrs	{isEnable=1 '\x01',isCacheable=1 '\x01',isBufferable=1 '\x01',isSharable=0 '\x00',isExecuteNever=...	0x70128924
			isEnable	unsigned char	1 '\x01'	0x70128924
			isCacheable	unsigned char	1 '\x01'	0x70128925
			isBufferable	unsigned char	1 '\x01'	0x70128926
			isSharable	unsigned char	0 '\x00'	0x70128927
			isExecuteNever	unsigned char	0 '\x00'	0x70128928
			tex	unsigned char	1 '\x01'	0x70128929
			accessPerm	unsigned char	2 '\x02'	0x7012892A
			subregionDisableMask	unsigned char	0 '\x00'	0x7012892B
	[2]	struct MpuP_RegionConfig_	{baseAddr=524288,size=14,attrs={isEnable=1 '\x01',isCacheable=1 '\x01',isBufferable=...}	0x7012892C
		baseAddr	unsigned int	524288	0x7012892C
		size	unsigned int	14	0x70128930
		attrs	struct MpuP_RegionAttrs	{isEnable=1 '\x01',isCacheable=1 '\x01',isBufferable=1 '\x01',isSharable=0 '\x00',isExecuteNever=...	0x70128934
			isEnable	unsigned char	1 '\x01'	0x70128934
			isCacheable	unsigned char	1 '\x01'	0x70128935
			isBufferable	unsigned char	1 '\x01'	0x70128936
			isSharable	unsigned char	0 '\x00'	0x70128937
			isExecuteNever	unsigned char	0 '\x00'	0x70128938
			tex	unsigned char	1 '\x01'	0x70128939
			accessPerm	unsigned char	2 '\x02'	0x7012893A
			subregionDisableMask	unsigned char	0 '\x00'	0x7012893B
	[3]	struct MpuP_RegionConfig_	{baseAddr=1879048192,size=20,attrs={isEnable=1 '\x01',isCacheable=1 '\x01',isBufferable=...}	0x7012893C
	[4]	struct MpuP_RegionConfig_	{baseAddr=1355808768,size=13,attrs={isEnable=1 '\x01',isCacheable=0 '\x00',isBufferable=...}	0x7012894C
	[5]	struct MpuP_RegionConfig_	{baseAddr=1912602624,size=13,attrs={isEnable=1 '\x01',isCacheable=0 '\x00',isBufferable=...}	0x7012895C
	[6]	struct MpuP_RegionConfig_	{baseAddr=1879048192,size=15,attrs={isEnable=1 '\x01',isCacheable=1 '\x01',isBufferable=...}	0x7012896C

Pelase advise.

Regads,

Tollman

0 Archit Dev 7 months ago in reply to TollMan

TI__Intellectual 2400 points

Hi TollMan,

Can you please share the PHY Register values in your case?

You can use the following GEL Script in order to get them on AM263Px : read_phy_reg.gel.

Regards
Archit Dev

0 TollMan 7 months ago in reply to Archit Dev

Intellectual 445 points

Hi Archit ,

I wasn't able to run the gel script you provided; I've never done this before. I tried loading it in CCS, and executing functions in the script through the console, but that doesn't seem to be the correct procedure to run the script.

Please provide a procedure to do this.

Thanks,

Tollman

0 Archit Dev 7 months ago in reply to TollMan

TI__Intellectual 2400 points

Hi TollMan,

In order to load the GEL file and read the PHY Registers, the following steps are followed usually:

1. Add GEL file using Tools > GEL Files > Right click in the table under the "GEL Files" tab > Click on "Load GEL..." option.
2. After initializing PHYs and ICSS MDIO, run the script from Scripts >ICSS_Configuration >PRU_ICSSG_PHY_Reg_Dump.
Post this step, the PHY Register values should be printed in the console.

I see that you are already done with the Step 1. Just perform the Step 2 mentioned above and you should get the PHY Register values in the console.

Regards
Archit Dev

0 TollMan 7 months ago in reply to Archit Dev

Intellectual 445 points

Hi Archit ,

Thanks for the help running the script. Here is the output after establishing link, and running a ICMP PING from the PC.

Cortex_R5_0: GEL Output:
ICSSG0 PHY0 Registers
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000000 Val : 0x00001140
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000001 Val : 0x0000796D
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000002 Val : 0x00002000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000003 Val : 0x0000A0F3
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000004 Val : 0x000001E1
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000005 Val : 0x00004DE1
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000006 Val : 0x00000067
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000007 Val : 0x00002001
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000008 Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000009 Val : 0x00000300
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000000A Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000000B Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000000C Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000000D Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000000E Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000000F Val : 0x0000F000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000010 Val : 0x00005048
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000011 Val : 0x00006C02
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000012 Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000013 Val : 0x00001C40
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000014 Val : 0x000029C7
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000015 Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000016 Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000017 Val : 0x00000040
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000018 Val : 0x00006150
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000019 Val : 0x00004444
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000001A Val : 0x00000002
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000001B Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000001C Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000001D Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000001E Val : 0x00000012
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x0000001F Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000467 Val : 0x00000000
Cortex_R5_0: GEL Output: PhyAddr: 0x00000000 Reg : 0x00000468 Val : 0x00000000
Cortex_R5_0: GEL Output:
ICSSG0 PHY1 Registers
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000000 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000001 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000002 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000003 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000004 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000005 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000006 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000007 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000008 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000009 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000000A Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000000B Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000000C Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000000D Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000000E Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000000F Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000010 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000011 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000012 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000013 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000014 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000015 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000016 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000017 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000018 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000019 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000001A Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000001B Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000001C Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000001D Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000001E Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x0000001F Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000467 Val : 0x0000FFFF
Cortex_R5_0: GEL Output: PhyAddr: 0x00000001 Reg : 0x00000468 Val : 0x0000FFFF

Regards,

Tollman

+1 Archit Dev 7 months ago in reply to TollMan

TI__Intellectual 2400 points

Hi TollMan,

Thanks for sharing the logs with us.

As suspected, from the PHY Register values, it looks like the PHY advertises and gets configured at 1G Speed and in RGMII mode.

We found that after the PHY Configuration was done in the application, a PHY reset happened which changed the PHY settings back to default according to the strap settings, leading to our PHY configuration not being reflected. This was leading to the issues.

Changing the Pinmux and PHY configuration sequence helped here. Moreover, there is a delay required for the Pinmux configuration changes to take effect.

These changes have been updated in the following file :

test_icss.c

/*
 * Copyright (C) 2024 Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 *
 *   Neither the name of Texas Instruments Incorporated nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */


/* lwIP core includes */
#include "ti_drivers_open_close.h"
#include "ti_drivers_config.h"
#include "ti_board_open_close.h"
#include "ti_board_config.h"

#include "lwip/opt.h"

#include <board/ethphy.h>
#include <board/eeprom.h>
#include <board/ethphy/ethphy_dp83826e.h>
#include <board/ethphy/ethphy_dp83869.h>
#ifdef SOC_AM263PX
#include <board/ioexp/ioexp_tca6424.h>
#endif

#include "test_icss_lwip.h"
#include "lwip2icss_emac.h"
#include "icss_emac.h"

#include <icss_emac_mmap.h>
#if ICSS_EMAC_MODE == ICSS_EMAC_MODE_SWITCH
#include <tiswitch_pruss_intc_mapping.h>
#else
#include <tiemac_pruicss_intc_mapping.h>
#endif

#ifdef AM263X_CC
#include <am263x-cc/pruicss_pinmux.h>
#elif AM263X_LP
#include <am263x-lp/pruicss_pinmux.h>
#elif AM263PX_CC
#include <am263px-cc/pruicss_pinmux.h>
#elif AM263PX_LP
#include <am263px-lp/pruicss_pinmux.h>
#endif


#include <drivers/hw_include/cslr_soc.h>
#ifdef SOC_AM263X
#include <drivers/hw_include/am263x/cslr_mss_ctrl.h>
#elif SOC_AM263PX
#include <drivers/hw_include/am263px/cslr_mss_ctrl.h>
#elif SOC_AM261X
#include <drivers/hw_include/am261x/cslr_mss_ctrl.h>
#endif

#include <drivers/pinmux.h>
#include<drivers/pruicss/m_v0/pruicss.h>
#include <drivers/hw_include/hw_types.h>

#if ICSS_EMAC_MODE == ICSS_EMAC_MODE_SWITCH
#include <icss_switch/mii/PRU0_bin.h>
#include <icss_switch/mii/PRU1_bin.h>
#else
#include <icss_dual_emac/mii/PRU0_bin.h>
#include <icss_dual_emac/mii/PRU1_bin.h>
#endif


/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

#define MSS_CTRL_ICSSM_PRU_GPIO_OUT_CTRL_VALUE  (0x0001077FU)

#define LWIPINIT_TASK_PRIORITY                  (8U)
#define LWIPINIT_TASK_STACK_SIZE                (0x4000U)

/*I2C Instance and Index for IO Expander programming*/
#define MDIO_MDC_MUX_SEL1                       (0x12U)
#define IO_EXP_I2C_INSTANCE                     (0x01U)

/*ICSS_EMAC Tx API Call Task*/
#define ICSS_EMAC_Tx_TASK_PRIORITY              (10U)
#define ICSS_EMAC_Tx_TASK_STACK_SIZE            (0x4000U)

#define ICSS_EMAC_MAXMTU                        (1518U)
#define ICSS_EMAC_TEST_PKT_TX_COUNT             (100U)

#if defined SOC_AM263X || defined SOC_AM263PX || defined (SOC_AM261X)
#define I2C_EEPROM_MAC0_DATA_OFFSET             (0x43U)
#else
#define I2C_EEPROM_MAC0_DATA_OFFSET             (0x3DU)
#endif

#define I2C_EEPROM_MAC1_DATA_OFFSET             (0x49U)

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

#if defined AM263X_LP || defined AM263PX_LP
void icssmMuxSelection(void);
#endif

#ifdef AM263PX_CC
void setIOExpMuxSelection(void *args);
#endif

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

uint32_t gtaskLwipInitStack[LWIPINIT_TASK_STACK_SIZE/sizeof(uint32_t)] __attribute__((aligned(32)));
TaskP_Object taskLwipInitObject;

uint32_t gtaskIcssEmacTxStack[ICSS_EMAC_Tx_TASK_STACK_SIZE/sizeof(uint32_t)] __attribute__((aligned(32)));
TaskP_Object taskIcssEmacTxObject;

uint8_t ICSS_EMAC_testPktPromiscuous[] = {
    0x02, 0xb0, 0xc3, 0xdd, 0xee, 0xff, /* broadcast mac */
    0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
    0x08, 0x06, 0x00, 0x01,
    0x08, 0x00, 0x06, 0x04, 0x00,0x01,
    0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
    0xc0, 0xa8, 0x01, 0x16,
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
    0xc0, 0xa8,0x01, 0x02,
    0x0,0x1,0x2,0x3,
    0x4,0x5,0x6,0x7,
    0x8,0x9,0xa,0xb,
    0xc,0xd,0xe,0xf,
    0x10,0x11,0x12,0x13,
    0x14,0x15,0x16,0x17,
    0x18,0x19,0x1a,0x1b,
    0x1c,0x1d,0x1e,0x1f,
    0x20,0x21,0x22,0x23,
    0x24,0x25,0x26,0x27,
    0x28,0x29,0x2a,0x2b,
    0x2c,0x2d,0x2e,0x2f,
    0x30,0x31,0x32,0x33,
    0x34,0x35,0x36,0x37,
    0x38,0x39,0x3a,0x3b,
    0x3c,0x3d,0x3e,0x3f,
    0x40,0x41,0x42,0x43,
    0x44,0x45,0x46,0x47,
    0x48,0x49,0x4a,0x4b,
    0x4c,0x4d,0x4e,0x4f,
    0x50,0x51,0x52,0x53,
    0x54,0x55,0x56,0x57,
    0x58,0x59,0x5a,0x5b,
    0x5c,0x5d,0x5e,0x5f,
    0x60,0x61,0x62,0x63,
    0x64,0x65,0x66,0x67,
    0x68,0x69,0x6a,0x6b,
    0x6c,0x6d,0x6e,0x6f,
    0x70,0x71,0x72,0x73,
    0x74,0x75,0x76,0x77,
    0x78,0x79,0x7a,0x7b,
    0x7c,0x7d,0x7e,0x7f,
    0x80,0x81,0x82,0x83,
    0x84,0x85,0x86,0x87,
    0x88,0x89,0x8a,0x8b,
    0x8c,0x8d,0x8e,0x8f,
    0x90,0x91,0x92,0x93,
    0x94,0x95,0x96,0x97,
    0x98,0x99,0x9a,0x9b,
    0x9c,0x9d,0x9e,0x9f,
    0xa0,0xa1,0xa2,0xa3,
    0xa4,0xa5,0xa6,0xa7,
    0xa8,0xa9,0xaa,0xab,
    0xac,0xad,0xae,0xaf,
    0xb0,0xb1,0xb2,0xb3,
    0xb4,0xb5,0xb6,0xb7,
    0xb8,0xb9,0xba,0xbb,
    0xbc,0xbd,0xbe,0xbf,
    0xc0,0xc1,0xc2,0xc3,
    0xc4,0xc5,0xc6,0xc7,
    0xc8,0xc9,0xca,0xcb,
    0xcc,0xcd,0xce,0xcf,
    0xd0,0xd1,0xd2,0xd3,
    0xd4,0xd5,0xd6,0xd7,
    0xd8,0xd9,0xda,0xdb,
    0xdc,0xdd,0xde,0xdf,
    0xe0,0xe1,0xe2,0xe3,
    0xe4,0xe5,0xe6,0xe7,
    0xe8,0xe9,0xea,0xeb,
    0xec,0xed,0xee,0xef,
    0xf0,0xf1,0xf2,0xf3,
    0xf4,0xf5,0xf6,0xf7,
    0xf8,0xf9,0xfa,0xfb,
    0xfc,0xfd,0xfe,0xff,
    0x0,0x1,0x2,0x3,
    0x4,0x5,0x6,0x7,
    0x8,0x9,0xa,0xb,
    0xc,0xd,0xe,0xf,
    0x10,0x11,0x12,0x13,
    0x14,0x15,0x16,0x17,
    0x18,0x19,0x1a,0x1b,
    0x1c,0x1d,0x1e,0x1f,
    0x20,0x21,0x22,0x23,
    0x24,0x25,0x26,0x27,
    0x28,0x29,0x2a,0x2b,
    0x2c,0x2d,0x2e,0x2f,
    0x30,0x31,0x32,0x33,
    0x34,0x35,0x36,0x37,
    0x38,0x39,0x3a,0x3b,
    0x3c,0x3d,0x3e,0x3f,
    0x40,0x41,0x42,0x43,
    0x44,0x45,0x46,0x47,
    0x48,0x49,0x4a,0x4b,
    0x4c,0x4d,0x4e,0x4f,
    0x50,0x51,0x52,0x53,
    0x54,0x55,0x56,0x57,
    0x58,0x59,0x5a,0x5b,
    0x5c,0x5d,0x5e,0x5f,
    0x60,0x61,0x62,0x63,
    0x64,0x65,0x66,0x67,
    0x68,0x69,0x6a,0x6b,
    0x6c,0x6d,0x6e,0x6f,
    0x70,0x71,0x72,0x73,
    0x74,0x75,0x76,0x77,
    0x78,0x79,0x7a,0x7b,
    0x7c,0x7d,0x7e,0x7f,
    0x80,0x81,0x82,0x83,
    0x84,0x85,0x86,0x87,
    0x88,0x89,0x8a,0x8b,
    0x8c,0x8d,0x8e,0x8f,
    0x90,0x91,0x92,0x93,
    0x94,0x95,0x96,0x97,
    0x98,0x99,0x9a,0x9b,
    0x9c,0x9d,0x9e,0x9f,
    0xa0,0xa1,0xa2,0xa3,
    0xa4,0xa5,0xa6,0xa7,
    0xa8,0xa9,0xaa,0xab,
    0xac,0xad,0xae,0xaf,
    0xb0,0xb1,0xb2,0xb3,
    0xb4,0xb5,0xb6,0xb7,
    0xb8,0xb9,0xba,0xbb,
    0xbc,0xbd,0xbe,0xbf,
    0xc0,0xc1,0xc2,0xc3,
    0xc4,0xc5,0xc6,0xc7,
    0xc8,0xc9,0xca,0xcb,
    0xcc,0xcd,0xce,0xcf,
    0xd0,0xd1,0xd2,0xd3,
    0xd4,0xd5,0xd6,0xd7,
    0xd8,0xd9,0xda,0xdb,
    0xdc,0xdd,0xde,0xdf,
    0xe0,0xe1,0xe2,0xe3,
    0xe4,0xe5,0xe6,0xe7,
    0xe8,0xe9,0xea,0xeb,
    0xec,0xed,0xee,0xef,
    0xf0,0xf1,0xf2,0xf3,
    0xf4,0xf5,0xf6,0xf7,
    0xf8,0xf9,0xfa,0xfb,
    0xfc,0xfd,0xfe,0xff,
    0x0,0x1,0x2,0x3,
    0x4,0x5,0x6,0x7,
    0x8,0x9,0xa,0xb,
    0xc,0xd,0xe,0xf,
    0x10,0x11,0x12,0x13,
    0x14,0x15,0x16,0x17,
    0x18,0x19,0x1a,0x1b,
    0x1c,0x1d,0x1e,0x1f,
    0x20,0x21,0x22,0x23,
    0x24,0x25,0x26,0x27,
    0x28,0x29,0x2a,0x2b,
    0x2c,0x2d,0x2e,0x2f,
    0x30,0x31,0x32,0x33,
    0x34,0x35,0x36,0x37,
    0x38,0x39,0x3a,0x3b,
    0x3c,0x3d,0x3e,0x3f,
    0x40,0x41,0x42,0x43,
    0x44,0x45,0x46,0x47,
    0x48,0x49,0x4a,0x4b,
    0x4c,0x4d,0x4e,0x4f,
    0x50,0x51,0x52,0x53,
    0x54,0x55,0x56,0x57,
    0x58,0x59,0x5a,0x5b,
    0x5c,0x5d,0x5e,0x5f,
    0x60,0x61,0x62,0x63,
    0x64,0x65,0x66,0x67,
    0x68,0x69,0x6a,0x6b,
    0x6c,0x6d,0x6e,0x6f,
    0x70,0x71,0x72,0x73,
    0x74,0x75,0x76,0x77,
    0x78,0x79,0x7a,0x7b,
    0x7c,0x7d,0x7e,0x7f,
    0x80,0x81,0x82,0x83,
    0x84,0x85,0x86,0x87,
    0x88,0x89,0x8a,0x8b,
    0x8c,0x8d,0x8e,0x8f,
    0x90,0x91,0x92,0x93,
    0x94,0x95,0x96,0x97,
    0x98,0x99,0x9a,0x9b,
    0x9c,0x9d,0x9e,0x9f,
    0xa0,0xa1,0xa2,0xa3,
    0xa4,0xa5,0xa6,0xa7,
    0xa8,0xa9,0xaa,0xab,
    0xac,0xad,0xae,0xaf,
    0xb0,0xb1,0xb2,0xb3,
    0xb4,0xb5,0xb6,0xb7,
    0xb8,0xb9,0xba,0xbb,
    0xbc,0xbd,0xbe,0xbf,
    0xc0,0xc1,0xc2,0xc3,
    0xc4,0xc5,0xc6,0xc7,
    0xc8,0xc9,0xca,0xcb,
    0xcc,0xcd,0xce,0xcf,
    0xd0,0xd1,0xd2,0xd3,
    0xd4,0xd5,0xd6,0xd7,
    0xd8,0xd9,0xda,0xdb,
    0xdc,0xdd,0xde,0xdf,
    0xe0,0xe1,0xe2,0xe3,
    0xe4,0xe5,0xe6,0xe7,
    0xe8,0xe9,0xea,0xeb,
    0xec,0xed,0xee,0xef,
    0xf0,0xf1,0xf2,0xf3,
    0xf4,0xf5,0xf6,0xf7,
    0xf8,0xf9,0xfa,0xfb,
    0xfc,0xfd,0xfe,0xff,
    0x0,0x1,0x2,0x3,
    0x4,0x5,0x6,0x7,
    0x8,0x9,0xa,0xb,
    0xc,0xd,0xe,0xf,
    0x10,0x11,0x12,0x13,
    0x14,0x15,0x16,0x17,
    0x18,0x19,0x1a,0x1b,
    0x1c,0x1d,0x1e,0x1f,
    0x20,0x21,0x22,0x23,
    0x24,0x25,0x26,0x27,
    0x28,0x29,0x2a,0x2b,
    0x2c,0x2d,0x2e,0x2f,
    0x30,0x31,0x32,0x33,
    0x34,0x35,0x36,0x37,
    0x38,0x39,0x3a,0x3b,
    0x3c,0x3d,0x3e,0x3f,
    0x40,0x41,0x42,0x43,
    0x44,0x45,0x46,0x47,
    0x48,0x49,0x4a,0x4b,
    0x4c,0x4d,0x4e,0x4f,
    0x50,0x51,0x52,0x53,
    0x54,0x55,0x56,0x57,
    0x58,0x59,0x5a,0x5b,
    0x5c,0x5d,0x5e,0x5f,
    0x60,0x61,0x62,0x63,
    0x64,0x65,0x66,0x67,
    0x68,0x69,0x6a,0x6b,
    0x6c,0x6d,0x6e,0x6f,
    0x70,0x71,0x72,0x73,
    0x74,0x75,0x76,0x77,
    0x78,0x79,0x7a,0x7b,
    0x7c,0x7d,0x7e,0x7f,
    0x80,0x81,0x82,0x83,
    0x84,0x85,0x86,0x87,
    0x88,0x89,0x8a,0x8b,
    0x8c,0x8d,0x8e,0x8f,
    0x90,0x91,0x92,0x93,
    0x94,0x95,0x96,0x97,
    0x98,0x99,0x9a,0x9b,
    0x9c,0x9d,0x9e,0x9f,
    0xa0,0xa1,0xa2,0xa3,
    0xa4,0xa5,0xa6,0xa7,
    0xa8,0xa9,0xaa,0xab,
    0xac,0xad,0xae,0xaf,
    0xb0,0xb1,0xb2,0xb3,
    0xb4,0xb5,0xb6,0xb7,
    0xb8,0xb9,0xba,0xbb,
    0xbc,0xbd,0xbe,0xbf,
    0xc0,0xc1,0xc2,0xc3,
    0xc4,0xc5,0xc6,0xc7,
    0xc8,0xc9,0xca,0xcb,
    0xcc,0xcd,0xce,0xcf,
    0xd0,0xd1,0xd2,0xd3,
    0xd4,0xd5,0xd6,0xd7,
    0xd8,0xd9,0xda,0xdb,
    0xdc,0xdd,0xde,0xdf,
    0xe0,0xe1,0xe2,0xe3,
    0xe4,0xe5,0xe6,0xe7,
    0xe8,0xe9,0xea,0xeb,
    0xec,0xed,0xee,0xef,
    0xf0,0xf1,0xf2,0xf3,
    0xf4,0xf5,0xf6,0xf7,
    0xf8,0xf9,0xfa,0xfb,
    0xfc,0xfd,0xfe,0xff,
    0x0,0x1,0x2,0x3,
    0x4,0x5,0x6,0x7,
    0x8,0x9,0xa,0xb,
    0xc,0xd,0xe,0xf,
    0x10,0x11,0x12,0x13,
    0x14,0x15,0x16,0x17,
    0x18,0x19,0x1a,0x1b,
    0x1c,0x1d,0x1e,0x1f,
    0x20,0x21,0x22,0x23,
    0x24,0x25,0x26,0x27,
    0x28,0x29,0x2a,0x2b,
    0x2c,0x2d,0x2e,0x2f,
    0x30,0x31,0x32,0x33,
    0x34,0x35,0x36,0x37,
    0x38,0x39,0x3a,0x3b,
    0x3c,0x3d,0x3e,0x3f,
    0x40,0x41,0x42,0x43,
    0x44,0x45,0x46,0x47,
    0x48,0x49,0x4a,0x4b,
    0x4c,0x4d,0x4e,0x4f,
    0x50,0x51,0x52,0x53,
    0x54,0x55,0x56,0x57,
    0x58,0x59,0x5a,0x5b,
    0x5c,0x5d,0x5e,0x5f,
    0x60,0x61,0x62,0x63,
    0x64,0x65,0x66,0x67,
    0x68,0x69,0x6a,0x6b,
    0x6c,0x6d,0x6e,0x6f,
    0x70,0x71,0x72,0x73,
    0x74,0x75,0x76,0x77,
    0x78,0x79,0x7a,0x7b,
    0x7c,0x7d,0x7e,0x7f,
    0x80,0x81,0x82,0x83,
    0x84,0x85,0x86,0x87,
    0x88,0x89,0x8a,0x8b,
    0x8c,0x8d,0x8e,0x8f,
    0x90,0x91,0x92,0x93,
    0x94,0x95,0x96,0x97,
    0x98,0x99,0x9a,0x9b,
    0x9c,0x9d,0x9e,0x9f,
    0xa0,0xa1,0xa2,0xa3,
    0xa4,0xa5,0xa6,0xa7,
    0xa8,0xa9,0xaa,0xab,
    0xac,0xad,0xae,0xaf,
    0xb0,0xb1,0xb2,0xb3,
    0xb4,0xb5,0xb6,0xb7,
    0xb8,0xb9,0xba,0xbb,
    0xbc,0xbd,0xbe,0xbf,
    0xc0,0xc1,0xc2,0xc3,
    0xc4,0xc5,0xc6,0xc7,
    0xc8,0xc9,0xca,0xcb,
    0xcc,0xcd,0xce,0xcf,
    0xd0,0xd1,0xd2,0xd3,
    0xd4,0xd5,0xd6,0xd7,
    0xd8,0xd9,0xda,0xdb,
    0xdc,0xdd,0xde,0xdf,
    0xe0,0xe1,0xe2,0xe3,
    0xe4,0xe5,0xe6,0xe7,
    0xe8,0xe9,0xea,0xeb,
    0xec,0xed,0xee,0xef,
    0xf0,0xf1,0xf2,0xf3,
    0xf4,0xf5,0xf6,0xf7,
    0xf8,0xf9,0xfa,0xfb,
    0xfc,0xfd,0xfe,0xff,
    0x0,0x1,0x2,0x3,
    0x4,0x5,0x6,0x7,
    0x8,0x9,0xa,0xb,
    0xc,0xd,0xe,0xf,
    0x10,0x11,0x12,0x13,
    0x14,0x15,0x16,0x17,
    0x18,0x19,0x1a,0x1b,
    0x1c,0x1d,0x1e,0x1f,
    0x20,0x21,0x22,0x23,
    0x24,0x25,0x26,0x27,
    0x28,0x29,0x2a,0x2b,
    0x2c,0x2d,0x2e,0x2f,
    0x30,0x31,0x32,0x33,
    0x34,0x35,0x36,0x37,
    0x38,0x39,0x3a,0x3b,
    0x3c,0x3d,0x3e,0x3f,
    0x40,0x41,0x42,0x43,
    0x44,0x45,0x46,0x47,
    0x48,0x49,0x4a,0x4b,
    0x4c,0x4d,0x4e,0x4f,
    0x50,0x51,0x52,0x53,
    0x54,0x55,0x56,0x57,
    0x58,0x59,0x5a,0x5b,
    0x5c,0x5d,0x5e,0x5f,
    0x60,0x61,0x62,0x63,
    0x64,0x65,0x66,0x67,
    0x68,0x69,0x6a,0x6b,
    0x6c,0x6d,0x6e,0x6f,
    0x70,0x71,0x72,0x73,
    0x74,0x75,0x76,0x77,
    0x78,0x79,0x7a,0x7b,
    0x7c,0x7d,0x7e,0x7f,
    0x80,0x81,0x82,0x83,
    0x84,0x85,0x86,0x87,
    0x88,0x89,0x8a,0x8b,
    0x8c,0x8d,0x8e,0x8f,
    0x90,0x91,0x92,0x93,
    0x94,0x95,0x96,0x97,
    0x98,0x99,0x9a,0x9b,
    0x9c,0x9d,0x9e,0x9f,
    0xa0,0xa1,0xa2,0xa3,
    0xa4,0xa5,0xa6,0xa7,
    0xa8,0xa9,0xaa,0xab,
    0xac,0xad,0xae,0xaf,
    0xb0,0xb1,0xb2,0xb3,
    0xb4,0xb5,0xb6,0xb7,
    0xb8,0xb9,0xba,0xbb,
    0xbc,0xbd,0xbe,0xbf,
    0xc0,0xc1,0xc2,0xc3,
    0xc4,0xc5,0xc6,0xc7,
    0xc8,0xc9,0xca,0xcb,
    0xcc,0xcd,0xce,0xcf,
    0xd0,0xd1,0xd2,0xd3,
    0xd4,0xd5,0xd6,0xd7,
    0xd8,0xd9,0xda,0xdb,
};

uint8_t ICSS_EMAC_testLclMac0[6];

/** \brief PRU-ICSS Handle */
PRUICSS_Handle pruicssHandle;

/** \brief ICSS EMAC Handle */
ICSS_EMAC_Handle icssemacHandle2;

extern void Lwip2Emac_getHandle(Lwip2Emac_Handle *AppLwipHandle);

/** \brief LwIP Interface Layer Handle */
Lwip2Emac_Handle lwipifHandle;

#ifdef AM263PX_CC
static TCA6424_Config  gTCA6424_Config;
#endif

void print_cpu_load()
{
    static uint32_t start_time = 0;
    uint32_t print_interval_in_secs = 5;
    uint32_t cur_time = ClockP_getTimeUsec()/1000;

    if(start_time==0)
    {
        start_time = cur_time;
    }
    else
    if( (cur_time-start_time) >= (print_interval_in_secs*1000) )
    {
        uint32_t cpu_load = TaskP_loadGetTotalCpuLoad();

        DebugP_log(" %6d.%3ds : CPU load = %3d.%02d %%\r\n",
            cur_time/1000, cur_time%1000,
            cpu_load/100, cpu_load%100 );

        start_time = cur_time;

        TaskP_loadResetAll();
    }
}

void ICSS_EMAC_testPinmuxConfig(void)
{
    Pinmux_config(gPruicssPinMuxCfg, PINMUX_DOMAIN_ID_MAIN);

    // Set bits for input pins in ICSSM_PRU0_GPIO_OUT_CTRL and ICSSM_PRU1_GPIO_OUT_CTRL registers
    HW_WR_REG32(CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_ICSSM_PRU0_GPIO_OUT_CTRL, MSS_CTRL_ICSSM_PRU_GPIO_OUT_CTRL_VALUE);
    HW_WR_REG32(CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_ICSSM_PRU1_GPIO_OUT_CTRL, MSS_CTRL_ICSSM_PRU_GPIO_OUT_CTRL_VALUE);

    DebugP_log("MII mode\r\n");

#if defined AM263X_LP || defined AM263PX_LP
    /* Setup GPIO for ICSSM MDIO Mux selection */
    icssmMuxSelection();
#else
    /* Set MDIO/MDC_MUX_SEL1 to low using IO Expander */
    setIOExpMuxSelection(NULL);
#endif

    /* Wait for the configuration changes to take effect */
    ClockP_sleep(1);
    /* MDIOALIVE register gets the value at this point. Required PHY Configuration can be done now. */
}

#if defined AM263X_CC || AM263PX_CC
void ICSS_EMAC_testPHYInitConfig(void)
{
    ETHPHY_DP83869_LedSourceConfig ledConfig0;
    ETHPHY_DP83869_LedBlinkRateConfig ledBlinkConfig0;
    ETHPHY_DP83826E_LedSourceConfig ledConfig1;
    ETHPHY_DP83826E_LedBlinkRateConfig ledBlinkConfig1;

    /* PHY pin LED_0 as link */
    ledConfig0.ledNum = ETHPHY_DP83869_LED0;
    ledConfig0.mode = ETHPHY_DP83869_LED_MODE_100BTX_LINK_UP;
    ledConfig1.ledNum = ETHPHY_DP83826E_LED0;
    ledConfig1.mode = ETHPHY_DP83826E_LED_MODE_MII_LINK_100BT_FD;
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig0, sizeof(ledConfig0));
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig1, sizeof(ledConfig1));

    /* PHY pin LED_1 indication is on if 1G link established for PHY0, and if 10M speed id configured for PHY1 */
    ledConfig0.ledNum = ETHPHY_DP83869_LED1;
    ledConfig0.mode = ETHPHY_DP83869_LED_MODE_1000BT_LINK_UP;
    ledConfig1.ledNum = ETHPHY_DP83826E_LED1;
    ledConfig1.mode = ETHPHY_DP83826E_LED_MODE_SPEED_10BT;
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig0, sizeof(ledConfig0));
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig1, sizeof(ledConfig1));

    /* PHY pin LED_2 as Rx/Tx Activity */
    ledConfig0.ledNum = ETHPHY_DP83869_LED2;
    ledConfig0.mode = ETHPHY_DP83869_LED_MODE_LINK_OK_AND_BLINK_ON_RX_TX;
    ledConfig1.ledNum = ETHPHY_DP83826E_LED2;
    ledConfig1.mode = ETHPHY_DP83826E_LED_MODE_LINK_OK_AND_BLINK_ON_RX_TX;
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig0, sizeof(ledConfig0));
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig1, sizeof(ledConfig1));

    ledBlinkConfig0.rate = ETHPHY_DP83869_LED_BLINK_RATE_200_MS;
    ledBlinkConfig1.rate = ETHPHY_DP83826E_LED_BLINK_RATE_200_MS;
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_CONFIGURE_LED_BLINK_RATE, (void *)&ledBlinkConfig0, sizeof(ledBlinkConfig0));
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_CONFIGURE_LED_BLINK_RATE, (void *)&ledBlinkConfig1, sizeof(ledBlinkConfig1));

    /* Enable MII mode for DP83869 PHY */
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_ENABLE_MII, NULL, 0);

    /* Disable 1G advertisement and soft-reset to restart auto-negotiation in case 1G link was establised */
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_DISABLE_1000M_ADVERTISEMENT, NULL, 0);
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_SOFT_RESTART, NULL, 0);

    /*Wait for PHY to come out of reset*/
    ClockP_sleep(1);
}
#else
void ICSS_EMAC_testPHYInitConfig(void)
{
    ETHPHY_DP83869_LedSourceConfig ledConfig;
    ETHPHY_DP83869_LedBlinkRateConfig ledBlinkConfig;

    /* PHY pin LED_0 as link */
    ledConfig.ledNum = ETHPHY_DP83869_LED0;
    ledConfig.mode = ETHPHY_DP83869_LED_MODE_100BTX_LINK_UP;
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig, sizeof(ledConfig));
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig, sizeof(ledConfig));

    /* PHY pin LED_1 indication is on if 1G link established for PHY0, and if 10M speed id configured for PHY1 */
    ledConfig.ledNum = ETHPHY_DP83869_LED1;
    ledConfig.mode = ETHPHY_DP83869_LED_MODE_1000BT_LINK_UP;
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig, sizeof(ledConfig));
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig, sizeof(ledConfig));

    /* PHY pin LED_2 as Rx/Tx Activity */
    ledConfig.ledNum = ETHPHY_DP83869_LED2;
    ledConfig.mode = ETHPHY_DP83869_LED_MODE_LINK_OK_AND_BLINK_ON_RX_TX;
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig, sizeof(ledConfig));
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_CONFIGURE_LED_SOURCE, (void *)&ledConfig, sizeof(ledConfig));

    ledBlinkConfig.rate = ETHPHY_DP83869_LED_BLINK_RATE_200_MS;
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_CONFIGURE_LED_BLINK_RATE, (void *)&ledBlinkConfig, sizeof(ledBlinkConfig));
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_CONFIGURE_LED_BLINK_RATE, (void *)&ledBlinkConfig, sizeof(ledBlinkConfig));

    /* Enable MII mode  */
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_ENABLE_MII, NULL, 0);
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_ENABLE_MII, NULL, 0);

    /* Disable 1G advertisement and soft-reset to restart auto-negotiation in case 1G link was establised */
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_DISABLE_1000M_ADVERTISEMENT, NULL, 0);
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_DISABLE_1000M_ADVERTISEMENT, NULL, 0);

    /* Soft-reset PHY */
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY0], ETHPHY_CMD_SOFT_RESTART, NULL, 0);
    ETHPHY_command(gEthPhyHandle[CONFIG_ETHPHY1], ETHPHY_CMD_SOFT_RESTART, NULL, 0);

    /*Wait for PHY to come out of reset*/
    ClockP_sleep(1);
}
#endif

int32_t ICSS_EMAC_testPruicssInstanceSetup(void)
{
    PRUICSS_IntcInitData    pruss_intc_initdata = PRUSS_INTC_INITDATA;
    ICSS_EMAC_Params        icssEmacParams;

    /*Getting Lwip2EmacHandle for interface layer*/
    Lwip2Emac_getHandle(&lwipifHandle);

    /*PRU2 ETH0 initializations*/
    ICSS_EMAC_Params_init(&icssEmacParams);
    icssEmacParams.pruicssIntcInitData = &pruss_intc_initdata;
    icssEmacParams.fwStaticMMap = &(icss_emacFwStaticCfg[1]);
    icssEmacParams.fwDynamicMMap = &icss_emacFwDynamicCfg;
    icssEmacParams.fwVlanFilterParams = &icss_emacFwVlanFilterCfg;
    icssEmacParams.fwMulticastFilterParams = &icss_emacFwMulticastFilterCfg;
    icssEmacParams.pruicssHandle = pruicssHandle;
    icssEmacParams.callBackObject.rxNRTCallBack.callBack = (ICSS_EMAC_CallBack)Lwip2Emac_serviceRx;
    icssEmacParams.callBackObject.rxNRTCallBack.userArg = (void*)(lwipifHandle);
    icssEmacParams.ethphyHandle[0] = gEthPhyHandle[CONFIG_ETHPHY0];
#if ICSS_EMAC_MODE == ICSS_EMAC_MODE_SWITCH
    icssEmacParams.ethphyHandle[1] = gEthPhyHandle[CONFIG_ETHPHY1];
#endif
    memcpy(&(icssEmacParams.macId[0]), &(ICSS_EMAC_testLclMac0[0]), 6);

    icssemacHandle2 = ICSS_EMAC_open(CONFIG_ICSS_EMAC0, &icssEmacParams);
    DebugP_assert(icssemacHandle2 != NULL);

    return 0;
}

int32_t app_getEmacHandle(Lwip2Emac_Handle hLwip2Emac)
{
    int32_t ret_val = SystemP_FAILURE;
    if(hLwip2Emac != NULL)
    {
        hLwip2Emac->emacHandle = icssemacHandle2;
        ret_val = SystemP_SUCCESS;
    }

    return (ret_val);
}

void ICSS_EMAC_testGetPruFwPtr(uint32_t *pru0FwPtr, uint32_t *pru0FwLength, uint32_t *pru1FwPtr, uint32_t *pru1FwLength)
{
    *pru0FwPtr = (uint32_t)&PRU0_b00[0];
    *pru0FwLength = (uint32_t)sizeof(PRU0_b00);
    *pru1FwPtr = (uint32_t)&PRU1_b00[0];
    *pru1FwLength = (uint32_t)sizeof(PRU1_b00);
}

void lwipIcss_socgetMACAddress()
{
    uint32_t status = SystemP_FAILURE;
    status = EEPROM_read(gEepromHandle[CONFIG_EEPROM0], I2C_EEPROM_MAC0_DATA_OFFSET, ICSS_EMAC_testLclMac0, 6U);
    DebugP_assert(SystemP_SUCCESS == status);
}

void ICSS_EMAC_testSetupRATConfig(void)
{
    uint32_t    icssBaseAddr;

    /* Setup RAT configuration for buffer region*/
    /* Setting up RAT config to map emacBaseAddr->l3OcmcBaseAddr to C30 constant of PRUICSS */
    /* Mapping 0xE0000000 (C30 constant of PRUICSS) to l3OcmcBaseAddr */
    icssBaseAddr = (uint32_t)((PRUICSS_HwAttrs *)(pruicssHandle->hwAttrs)->baseAddr);

    HW_WR_REG32(icssBaseAddr + CSL_ICSS_RAT_REGS_0_BASE + 0x24, (0xE0000000));         /*rat0 base0 */
    HW_WR_REG32(icssBaseAddr + CSL_ICSS_RAT_REGS_0_BASE + 0x28, (0x70000000));         /*rat0 trans_low0 */
    HW_WR_REG32(icssBaseAddr + CSL_ICSS_RAT_REGS_0_BASE + 0x2C, (0x00000000));         /*rat0 trans_low0 */
    HW_WR_REG32(icssBaseAddr + CSL_ICSS_RAT_REGS_0_BASE + 0x20, (1u << 31) | (22));    /*rat0 ctrl0 */

    HW_WR_REG32(icssBaseAddr + CSL_ICSS_RAT_REGS_1_BASE + 0x24, (0xE0000000));         /*rat0 base0 */
    HW_WR_REG32(icssBaseAddr + CSL_ICSS_RAT_REGS_1_BASE + 0x28, (0x70000000));         /*rat0 trans_low0 */
    HW_WR_REG32(icssBaseAddr + CSL_ICSS_RAT_REGS_1_BASE + 0x2C, (0x00000000));         /*rat0 trans_low0 */
    HW_WR_REG32(icssBaseAddr + CSL_ICSS_RAT_REGS_1_BASE + 0x20, (1u << 31) | (22));    /*rat0 ctrl0 */
}

int32_t ICSS_EMAC_testLoadPRUFirmware(void)
{
    int32_t     retVal          =   SystemP_FAILURE;
    uint32_t    result_flag     =   0;
    uint32_t    pru0FwPtr       =   0;
    uint32_t    pru0FwLength    =   0;
    uint32_t    pru1FwPtr       =   0;
    uint32_t    pru1FwLength    =   0;

    PRUICSS_disableCore(pruicssHandle, PRUICSS_PRU0);
    PRUICSS_disableCore(pruicssHandle, PRUICSS_PRU1);

    ICSS_EMAC_testGetPruFwPtr(&pru0FwPtr, &pru0FwLength, &pru1FwPtr, &pru1FwLength);

    result_flag = PRUICSS_writeMemory(pruicssHandle, PRUICSS_IRAM_PRU(0), 0, (uint32_t *)pru0FwPtr, pru0FwLength);
    if(result_flag)
    {
        DebugP_log("Firmware load to PRU0 passed\r\n");
        retVal = SystemP_SUCCESS;
    }
    else
    {
        DebugP_log("Firmware load to PRU0 failed\r\n");
        retVal = SystemP_FAILURE;
    }

    result_flag = PRUICSS_writeMemory(pruicssHandle, PRUICSS_IRAM_PRU(1), 0, (uint32_t *)pru1FwPtr, pru1FwLength);
    if(result_flag && retVal == SystemP_SUCCESS)
    {
        DebugP_log("Firmware load to PRU1 passed\r\n");
        retVal = SystemP_SUCCESS;
    }
    else
    {
        DebugP_log("Firmware load to PRU1 failed\r\n");
        retVal = SystemP_FAILURE;
    }

    if(retVal == SystemP_SUCCESS)
    {
        PRUICSS_enableCore(pruicssHandle, PRUICSS_PRU0);
        PRUICSS_enableCore(pruicssHandle, PRUICSS_PRU1);
    }

    return retVal;
}
    
int icss_lwip_example(void *args)
{
    uint32_t                status = SystemP_FAILURE;

    Drivers_open();
    status = Board_driversOpen();
    DebugP_assert(status==SystemP_SUCCESS);

    /* Perform the Pinmux config */
    ICSS_EMAC_testPinmuxConfig();

    /* Perform PRUICSS Open */
    pruicssHandle = PRUICSS_open(CONFIG_PRU_ICSS1);
    DebugP_assert(pruicssHandle != NULL);

    /* Setup the local MAC Addresses of Port from EEPROM */
    lwipIcss_socgetMACAddress();
    ICSS_EMAC_testPruicssInstanceSetup();

    /* Setup RAT configuration for buffer region */
    ICSS_EMAC_testSetupRATConfig();

    /* Load the PRU Firmware */
    status = ICSS_EMAC_testLoadPRUFirmware();
    DebugP_assert(status==SystemP_SUCCESS);

    /* Perform the PHY Configuration */
    ICSS_EMAC_testPHYInitConfig();

    /* Start the main loop */
    main_loop(NULL);

    return 0;
}

#if defined AM263X_LP || defined AM263PX_LP
void icssmMuxSelection(void)
{
    uint32_t pinNum[CONFIG_GPIO_NUM_INSTANCES] = {CONFIG_GPIO0_PIN, CONFIG_GPIO1_PIN, CONFIG_GPIO2_PIN};
    uint32_t pinDir[CONFIG_GPIO_NUM_INSTANCES] = {CONFIG_GPIO0_DIR, CONFIG_GPIO1_DIR, CONFIG_GPIO2_DIR};

    for(uint32_t index = 0; index < CONFIG_GPIO_NUM_INSTANCES-1; index++)
    {
        /* Address translate */
        uint32_t gGpioBaseAddr = (uint32_t) AddrTranslateP_getLocalAddr(CONFIG_GPIO0_BASE_ADDR);

        /* Setup GPIO for ICSSM MDIO Mux selection */
        GPIO_setDirMode(gGpioBaseAddr, pinNum[index], pinDir[index]);
        GPIO_pinWriteHigh(gGpioBaseAddr, pinNum[index]);
    }
}
#endif

#ifdef AM263PX_CC
/* Set MDIO/MDC_MUX_SEL1 to low using IO Expander to configure:
 *  On-Board PHY               ->  PRU0 MII0
 *  ETHERNET ADD-ON CONNECTOR  ->  PRU1 MII1
 *
 * Refer to Ethernet Routing in AM263Px User Guide for more details
 */
void setIOExpMuxSelection(void *args)
{
    int32_t             status = SystemP_SUCCESS;
    uint32_t            ioIndex = MDIO_MDC_MUX_SEL1;
    TCA6424_Params      tca6424Params;

    TCA6424_Params_init(&tca6424Params);

    tca6424Params.i2cInstance = IO_EXP_I2C_INSTANCE;

    status = TCA6424_open(&gTCA6424_Config, &tca6424Params);

    if(status == SystemP_SUCCESS)
    {
        /* Configure as output  */
        status = TCA6424_config(
                      &gTCA6424_Config,
                      ioIndex,
                      TCA6424_MODE_OUTPUT);

        /* set P22 low which controls MDIO/MDC_MUX_SEL1 -> enable PRU0_MII0 and PRU1_MII1 */
        status = TCA6424_setOutput(
                     &gTCA6424_Config,
                     ioIndex,
                     TCA6424_OUT_STATE_LOW);

    }
    TCA6424_close(&gTCA6424_Config);
}
#endif

.

You can replace the original "test_icss.c" with the attached file at: MCU_PLUS_SDK_INSTALL_PATH/examples/networking/lwip/icss_emac_lwip/test_icss.c

Regards
Archit Dev

0 TollMan 7 months ago in reply to Archit Dev

Intellectual 445 points

After applying the changes to "test_icss.c", I was able to ping the Control Card.

Thanks Archit.

Regards,

Tollman

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MCU-PLUS-SDK-AM263PX: AM263Px MCU+ SDK: ICSS-EMAC Lwip Example Transmit Error