• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 31 subscribers
  • Views 126 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2431: There is something unclear about TRM "6.2.3.5.5 VIM Interrupt Prioritization"

?? ??
Intellectual 705 points
Part Number: AM2431

Tool/software:

The TRM refers to spruim2g.pdf

TRM "6.2.3.5.5 VIM Interrupt Prioritization" states, "If prior to this interrupt being cleared (by writing to the R5FSS_VIM_FIQVEC register, or R5FSS_VIM_IRQVEC register) another interrupt of higher priority arrives,".

However, when I checked TRM "6.2.4.4.8 R5FSS_VIM_FIQVEC Register" and TRM "6.2.4.4.7 R5FSS_VIM_IRQVEC Register," I found that both the R5FSS_VIM_FIQVEC register and R5FSS_VIM_IRQVEC are read-only registers.
In the text it says "(by writing to the R5FSS_VIM_FIQVEC register, or R5FSS_VIM_IRQVEC register)", but I would like to know what it means to write to a read-only register.

Thank you in advance for your help.

  • 0
    TI__Mastermind 39541 points

    Hello ,

    I am looking at your queries and you may expect reply in one or two days .

    Regards,

    Anil.

  • 0
    Intellectual 705 points

    Sorry for the inconvenience.

    I have many questions and the threads are getting longer, so I would like to add a question to this thread.

    The TRM uses both CPU0 and CORE0, but I interpret them as meaning there is no difference.

    Is this interpretation correct?

    If I'm wrong, please explain how they are different.

    If they are the same, please tell me why CPU0 and CORE0 are used.

    Also, in TRM "6.2.3.5.4 VIM Interrupt Vector Table (VIM RAM)", it says "Note that both interrupt vector tables are identical in their memory organization."

    I have two questions about this sentence.

    -Does the "both interrupt vector tables" referred to in the sentence refer to CPU0 of R5FSSn and CPU1 of R5FSSn?

    Or does it refer to R5FSS0 and R5FSS1?

    -I would like to know what "are identical in their memory organization." specifically means.

    Original thread:
    e2e.ti.com/.../am2431-there-is-something-unclear-about-trm-6-2-3-5-4-vim-interrupt-vector-table-vim-ram

    Thank you in advance.

  • 0 in reply to Swargam Anil
    TI__Mastermind 37878 points

    Hello,

    Thanks for your patience.

    ?? ?? said:
    but I would like to know what it means to write to a read-only register.

    The above mentioned registers are read only register as you can see this details in register description table also.

    Writing any value to this register will not alter its contents, but will have the following effect:

    - Remove the mask on all IRQ priorities

    - This field is only valid if the R5FSS_VIM_PRIIRQ[31] VALID flag is set.

    Please refer below image for details.

    Regards,

    Tushar

  • 0 in reply to Tushar Thakur
    Intellectual 705 points

    Thank you for your reply. I will check your reply.

    I have an additional question.

    In TRM "6.2.3.5.8.2 Servicing IRQ Through MMR Interface", it says "When an IRQ interrupt is received, the CPU should follow these steps if not using the vector interface:".

    When using the vector interface, I understand that the current interrupt processing method refers to a vector table registered in advance, and the interrupt processing routine is called and processed.

    Therefore, I understand that the "vector interface" is an interface with interrupt processing using a vector table, but is this understanding correct?

    If the above understanding is correct, I would like to know how the interrupt processing can be executed with "if not using the vector interface" in the text, as I do not understand it.

    Original thread:
    e2e.ti.com/.../am2431-there-is-something-unclear-about-trm-6-2-3-5-8-2-servicing-irq-through-mmr-interface

    Thank you in advance.

  • 0 in reply to ?? ??
    TI__Mastermind 37878 points

    Hi 

    ?? ?? said:
    When using the vector interface, I understand that the current interrupt processing method refers to a vector table registered in advance, and the interrupt processing routine is called and processed.

    Yes, the above understanding is correct.

    ?? ?? said:
    If the above understanding is correct, I would like to know how the interrupt processing can be executed with "if not using the vector interface" in the text, as I do not understand it

    You can read the steps mentioned in section 6.2.3.5.8.2 Servicing IRQ Through MMR Interface of TRM for this details.

    When not using vector interface, CPU will read the R5FSS_VIM_IRQVEC register and jump to that address to service the ISR unlike the handshake method which is followed while servicing through vector interface.

    You do not need to bother about this steps as this is already been taken care in SDK. Can you please tell what is the use case?

    Regards,

    Tushar