SIMPLELINK-MSP432-SDK: MSP432P4111: use of WDT in LPM3/3.5

Hi,

  I'm trying to learn this device as a new device while I'm replying you. Please understand this is a obsolete device and the technical knowledge for this device is limited.  

Antonio Ricciardi said:

Use case: WDT in LPM3.5

Antonio Ricciardi said:

I would like to use this device to reset my system in case of a freeze or hang have been detected. As per datasheet (SLAU356I/2019), when in LPM3/3.5 it can be used only in interval time mode. The strategy is to reset the timer by tasks and do a system reset (via callback) once the timer expired.

Q1) Is this the best strategy or is there any suggestion?

During LPM3.5, all peripherals are powered down. Upon device wakeup from LPM3.5, you must go through a reset in order to bring the peripherals into a known state. I don't see an issue with your strategy to generate a system reset once the timer expired. 

17.2.6.4 WDT_A Operation in LPM3.5 Mode
The WDT_A remains functional in the LPM3.5 mode of operation. However, it may be used only in
interval timer mode. This is because there is no execution activity to handle the watchdog. On the other
hand, if the WDT_A is configured as an interval timer, the interval timer event can be used to wake up the
device back to active mode.
Before invoking the device entry to LPM3.5 mode, the WDT_A must be configured to use either BCLK or
VLOCLK as the source. If any of the other clock sources are used, the WDT_A may prevent the device
from entering LPM3.5 mode and the device will consume excess current as a result. Refer to the Power
Control Manager (PCM) chapter for more details about the clock handling during entry to low-power
modes.
Upon exit from LPM3.5 mode to active mode, the device undergoes a reset, but the WDT_A remains
functional and unaffected by the reset. This isolation is carried out through the LOCKBKUP and
LOCKLPM5 bits in the PCM. Refer to the PCM chapter for more details on entering and exiting LPM3.5
mode of operation.

8.4.4 LPM3.5 and LPM4.5
LPM3.5 and LPM4.5 modes provide the lowest power consumption possible but at reduced functionality.
In LPM3.5 mode, all peripherals are disabled and powered down except for the RTC and WDT, which can
be optionally enabled by the application and clocked out of low-frequency clock sources (LFXT, REFO,
and VLO). Furthermore, the device is brought down to the core voltage level 0. Wake up is possible
through any of the wake-up events mentioned in Table 8-10. LPM3.5 mode does not retain any
peripheral register data. In LPM3.5 mode however, depending on the SRAM organization, Bank 0 or
Block 0 of SRAM is retained for application's use as a backup memory and also device I/O pin
states are latched and retained.

Antonio Ricciardi said:

Q2) Also the example in the sdk folder under driver/watchdog is not goind in any LPM. The issue should be that "ti_drivers_config.c" select ACLK as clock source instead of BLCK or VLOCLK. Any suggestion on how to fix it?

I will suggest you overwrite the clock source. First method I can think of is to directly write to the WDTCLK register after the WDT initialization is done by TI-RTOS. The second method is to modify ti_drivers config.c to take BCLK as the source for WDT. But I think each time you regenerate new code, ti_drivers_config.c will be reverted back to its default selection. 

Antonio Ricciardi said:

Q3) Once in LPM3/3.5 and no active tasks, I expect that timeout/reset occurs as no one is resetting the timer. I would like to use the RTC to wake-up the system and do a timer reset but no driver/sysconfig seems available.

If this is the case I will suggest you directly configure the RTC module. You can reference this example at C:\ti\simplelink_msp432p4_sdk_3_40_01_02\examples\rtos\MSP_EXP432P401R\demos\cmsis_dsplib_ulp. In this example, the RTC is used to wake the device from deep sleep 0 (LPM3).

Antonio Ricciardi said:

Q4) Is the "SysCtl_A_rebootDevice()" the best call to reset?

Yes, I believe so. 

Antonio Ricciardi said:

Q5) How strenght is this solution compared to a pure watchdog used in active mode/lpm0? It can be a fail of BLCK or VLOCLK sources?

I can argue the same for LPM0 where ACLK is dead and WDT_T never counts to reset unless you have some diagnostic check between different clocks or a on-chip clock fail detection circuit to ensure clocks are functioning before WD is enabled. What if the clock source for WD becomes dead in the middle of WD counting? It depends on your functional safety requirements. You might need to consider an external WD then. 

Antonio Ricciardi said:

Q6) In general, the above config and verison is the best we can have for this pn?

Correct. There is no plan to upgrade the SDK for this PN and simplelink_msp432p4_sdk_3_40_01_02 is the final version. 

Many thanks for your feedback: finally I was able to use WDT in LPM3.5 manually fixing its clock soource; the same for RTC, I was able to use it by direct config.