Hello Haining,
As I mentioned above, the MAIN2MCU PSC and MCU2MAIN PSC are disabled, then cross domain functionality does not work out.
These changes are available in the SOC_enableResetIsolation API and other than this we are not doing changes in anywhere.
If you integrate SOC_enableResetIsolation and resetReqIsr API's in your application, all Reset Isolation changes were taken and user no need to take any other changes.
One more thing in the SBL we need to check the M4F core is Isolated or not if it is Isolated then we are not supposed to re init the M4F core clock configurations for every WarmReset. This is already taken care in SBL. So, again users don't need to consider any other steps.
Regards,
Anil.
in Sitara AM2434 Safety Manual there is a description about "Physical Isolation of MCU domain from Main domain".
Our goal is to make sure that Main domain should not access the peripherals of MCU domain.
I also find an example mcu_plus_sdk_am243x/examples/drivers/safety/reset_isolation/reset_isolation_mcu_domain.c and the call of function SOC_enableResetIsolation(...) wirh the following paramenter.
/* Disabling Main2MCU PSC. This would restrict the main domain from accessingMCU domain peripherals/registers. Care must be taken no Main domain cores accessMCU domain registers after this */pscMain2MCUDisable = 1;I try to integrate the code into out project in C++ and try to access GPIO pin from Main domain. It seems that the Isolation does not work. The GPIO can still be toggled.
Can You help me to find, what I do wrong. Or how it should be configured.
The class files are uploaded
/* * SitaraMcuIsolation.cpp * * Created on: 26.11.2024 * Author: zhih */ #include <sciopta.h> #include "SitaraMcuIsolation.hpp" #include "rat.h" namespace balluff { namespace bni_safe { namespace pal { namespace sitara { SitaraMcuIsolation::SitaraMcuIsolation() { util::SafeReturn status = util::SafeReturn::RET_ERROR; uint32_t pscMain2MCUDisable, pscMCU2MainDisable, debugIsolationEnable; /* Disabling Main2MCU PSC. This would restrict the main domain from accessing MCU domain peripherals/registers. Care must be taken no Main domain cores access MCU domain registers after this */ pscMain2MCUDisable = 1; /* Disabling MCU2Main PSC. This would restrict the MCU domain from accessing Main domain peripherals/registers. Care must be taken no MCU domain cores access Main domain registers after this */ pscMCU2MainDisable = 0; /* Enabling debug isolation will restrict the JTAG access to MCU domain */ debugIsolationEnable = 0; status = enableResetIsolation(pscMain2MCUDisable, pscMCU2MainDisable, debugIsolationEnable); kprintf(0, "SitaraMcuIsolation::SitaraMcuIsolation: status %x\n", status); } SitaraMcuIsolation::~SitaraMcuIsolation() { // TODO Auto-generated destructor stub } util::SafeReturn SitaraMcuIsolation::enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t debugIsolationEnable) { uint32_t baseAddr = 0; util::SafeReturn status = util::SafeReturn::RET_OK; controlModuleUnlockMMR(6); controlModuleUnlockMMR(1); baseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CSL_MCU_CTRL_MMR0_CFG0_BASE); /* Block MAIN domain reset: set bit 18 of CTRLMMR_RST_CTRL to 1.*/ REG32_FINS(baseAddr + CSL_MCU_CTRL_MMR_CFG0_RST_CTRL, 0x0040000U, 0x00000012U, 1); /* Enable timeout gasket */ REG32_FINS(baseAddr + CSL_MCU_CTRL_MMR_CFG0_MCU_MTOG_CTRL, 0x00008000U, 0x0000000FU, 1); /* Write a non zero value to Magic Word */ REG32_WR(baseAddr + CSL_MCU_CTRL_MMR_CFG0_RST_MAGIC_WORD, 0x1); if (debugIsolationEnable == 1) { /* Enable debug Isolation */ REG32_FINS(baseAddr + CSL_MCU_CTRL_MMR_CFG0_ISO_CTRL, 2, 1, 1); } /* Enable reset Isolation */ REG32_FINS(baseAddr + CSL_MCU_CTRL_MMR_CFG0_ISO_CTRL, 1, 0, 1); /* Block DMSC to trigger reset of MCU domain: set bit 16 of CTRLMMR_RST_CTRL to 1.*/ REG32_FINS(baseAddr + CSL_MCU_CTRL_MMR_CFG0_RST_CTRL, 0x00010000U, 0x00000010U, 1); if (main2McuIsolation == 1) { status = setPSCState(CSL_MCU_LPSC_MAIN2MCU, SOC_PSC_DISABLE); } if (status == util::SafeReturn::RET_OK) { if (mcu2MainIsolation == 1) { status = setPSCState(CSL_MCU_LPSC_MCU2MAIN, SOC_PSC_DISABLE); } } controlModuleLockMMR(6); controlModuleLockMMR(1); return status; } util::SafeReturn SitaraMcuIsolation::setPSCState(uint32_t moduleNum, uint32_t pscState) // 032 { util::SafeReturn status = util::SafeReturn::RET_OK; uint32_t baseAddr = 0; uint32_t loopCnt = 0; uint32_t pdTransStatus; baseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CSL_MCU_PSC0_BASE); if (status == util::SafeReturn::RET_OK) { /* get value of bits 0-5 of PSC0_MDSTAT Register*/ if (REG32_FEXT(baseAddr + CSL_MCU_PSC0_MDSTAT, 0x0000003FU, 0x00000000U) == pscState) { ; } else { if (pscState == PSC_MODSTATE_ENABLE) { /* Power Domain Control: set bit NEXT to 1 */ REG32_FINS(baseAddr + CSL_MCU_PSC0_PDCTL, 1, 0, 1); } /* Enable the clock for the module: Module Next State: set bits 0-4 of NEXT to 2 */ REG32_FINS(baseAddr + CSL_MCU_PSC0_MDCTL, 0x1F, 0, pscState); /* Start the state transition */ /* write 1 at PSC_PTCMD */ REG32_WR(baseAddr + CSL_MCU_PSC0_PTCMD, 1); /* check pdTransStatus(Power Domain n Transition Command Status) until it is set */ do { pdTransStatus = REG32_RD(baseAddr + CSL_MCU_PSC0_PTSTAT) & 1U; loopCnt++; } while (pdTransStatus && (loopCnt < PSC_TIMEOUT)); if (pdTransStatus == 0) { status = util::SafeReturn::RET_OK; } else { status = util::SafeReturn::RET_ERROR; } } } return status; } void SitaraMcuIsolation::controlModuleLockMMR(uint32_t partition) { uint32_t baseAddr; uint32_t kickAddr; baseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CSL_MCU_CTRL_MMR0_CFG0_BASE); kickAddr = baseAddr + (0x1008 + 0x4000 * (partition)); REG32_WR(kickAddr, KICK_LOCK_VAL); /* KICK 0 */ kickAddr++; REG32_WR(kickAddr, KICK_LOCK_VAL); /* KICK 1 */ return; } void SitaraMcuIsolation::controlModuleUnlockMMR(uint32_t partition) { uint32_t baseAddr; uint32_t kickAddr; baseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CSL_MCU_CTRL_MMR0_CFG0_BASE); kickAddr = baseAddr + (0x1008 + 0x4000 * (partition)); REG32_WR(kickAddr, KICK0_UNLOCK_VAL); /* KICK 0 */ kickAddr++; REG32_WR(kickAddr, KICK1_UNLOCK_VAL); /* KICK 1 */ return; } } // namespace sitara } // namespace pal } // namespace bni_safe } // namespace balluff/* * SitaraMcuIsolation.hpp * * Created on: 26.11.2024 * Author: zhih */ #ifndef SITARAMCUISOLATION_HPP_ #define SITARAMCUISOLATION_HPP_ #include "CommonTypes.hpp" namespace balluff { namespace bni_safe { namespace pal { namespace sitara { class SitaraMcuIsolation { public: SitaraMcuIsolation(); ~SitaraMcuIsolation(); private: util::SafeReturn enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t debugIsolationEnable); util::SafeReturn setPSCState(uint32_t moduleNum, uint32_t pscState); void controlModuleLockMMR(uint32_t partition); void controlModuleUnlockMMR(uint32_t partition); static uint32_t REG32_RD(uint32_t addr) { volatile uint32_t* const p = (volatile uint32_t*)addr; return (*p); } static void REG32_WR(uint32_t addr, uint32_t v) { volatile uint32_t* const p = (volatile uint32_t*)addr; *p = v; return; } static void REG32_FINS(uint32_t addr, uint32_t mask, uint32_t shift, uint32_t v) { uint32_t regVal = REG32_RD(addr); regVal = (regVal & ~(mask)); regVal |= (v << shift) & mask; REG32_WR(addr, regVal); return; } static uint32_t REG32_FEXT(uint32_t addr, uint32_t mask, uint32_t shift) { uint32_t regVal = REG32_RD(addr); regVal = (regVal & mask) >> shift; return (regVal); } static constexpr uint32_t CSL_MCU_CTRL_MMR0_CFG0_BASE = 0x04500000U; static constexpr uint32_t CSL_MCU_CTRL_MMR_CFG0_MCU_MTOG_CTRL = 0x00004600U; static constexpr uint32_t CSL_MCU_CTRL_MMR_CFG0_RST_CTRL = 0x00018170U; static constexpr uint32_t CSL_MCU_CTRL_MMR_CFG0_RST_MAGIC_WORD = 0x0001817CU; static constexpr uint32_t CSL_MCU_CTRL_MMR_CFG0_ISO_CTRL = 0x00018180U; static constexpr uint32_t CSL_MCU_PSC0_BASE = 0x04000000U; static constexpr uint32_t CSL_MCU_PSC0_PTCMD = 0x00000120U; static constexpr uint32_t CSL_MCU_PSC0_PTSTAT = 0x00000128U; static constexpr uint32_t CSL_MCU_PSC0_PDCTL = 0x00000300U; static constexpr uint32_t CSL_MCU_PSC0_MDSTAT = 0x0000080CU; static constexpr uint32_t CSL_MCU_PSC0_MDCTL = 0x00000A00U; static constexpr uint32_t SOC_PSC_SYNCRESETDISABLE = 0x0U; static constexpr uint32_t SOC_PSC_SYNCRESET = 0x1U; static constexpr uint32_t SOC_PSC_DISABLE = 0x2U; static constexpr uint32_t SOC_PSC_ENABLE = 0x3U; /* * MCU LPSC */ static constexpr uint32_t CSL_MCU_LPSC_MAIN2MCU = 0x3U; static constexpr uint32_t CSL_MCU_LPSC_MCU2MAIN = 0x4U; /* PSC (Power Sleep Controller) timeout */ static constexpr uint32_t PSC_TIMEOUT = 1000U; /* PSC (Power Sleep Controller) Domain enable */ static constexpr uint32_t PSC_MODSTATE_ENABLE = 0x3U; /* define the unlock and lock values */ static constexpr uint32_t KICK_LOCK_VAL = 0x00000000U; static constexpr uint32_t KICK0_UNLOCK_VAL = 0x68EF3490U; static constexpr uint32_t KICK1_UNLOCK_VAL = 0xD172BC5AU; }; } // namespace sitara } // namespace pal } // namespace bni_safe } // namespace balluff #endif /* SITARAMCUISOLATION_HPP_ */Best Regards
Haining Zhi