Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hi,
My customer wants to know how to set 64bit configuration for outbound of PCIe.
Normally, there are six of “BAR”s (index=0 to 5) for PCIe addresses translation and one “BAR” is 32-bit, so 64-bit PCIe address space can be accessed by using two consecutive BARs. For 64-bit access, a combination of BAR0 and BAR1, BAR2 and BAR3, or BAR4 and BAR5 is used.
The customer wants to access PCIe 64bit address space from AM243x by directly configuring “BAR” without SysCfg tool, but don’t understand how to set BAR0 and BAR1.
Could you tell them that ?
They're using MCU+ SDK 9.02.
To be specific, PCIe driver uses the structure “Pcie_ObAtuCfg” to set it up.
As only BAR0 is used in the case of accessing PCIe 32-bit address space,
if set like below,
Destination PCIe address = 0x7000_0000
reginWindowSize = 0x3FF_FFFF
and then,
The structure “Pcie_ObAtuCfg” would have only one array member like below.
On the other hand, they think that two of BAR0 and BAR1 must be used in the case of accessing PCIe 64-bit address space.
Destination PCIe address = 0x0006_7000_0000
ReginWindowSize = 0x3FF_FFFF
And then
Should they set two array members of the structure “Pcie_ObAtuCfg” ?
For example, like below
Alternatively, is BAR1 automatically set and used when BAR0 is set ?
However, it seemed to be 32bit PCIe address when they tried to set only BAR0.
Thanks and regards,
Hideaki
