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TMS570LC4357: Purpose and Implications of Disabling GCLK1 Domain on TMS570LC4357, and Impact on Interrupts

Part Number: TMS570LC4357

Tool/software:

Dear TI Support,

I am currently working with the TMS570LC4357 microcontroller and came across the CDDIS (Clock Domain Disable) register, particularly the bit related to the GCLK1 domain (SETGCLK1OFF). According to the documentation, this bit can disable the GCLK1 domain, which I understand is feeding critical components such as the CPU and CCM.

Specific Questions:

  1. Purpose: What is the intended use case or purpose for disabling the GCLK1 domain? Under what scenarios should this bit be toggled?
  2. Impacts: If the GCLK1 domain is disabled by setting this bit, should we expect an immediate halt of the CPU and other critical system functions? What safeguards are implemented to handle such an event?
  3. Interrupts: Considering the CPU relies on the GCLK1 domain, if the GCLK1 domain is disabled, how are interrupts affected? Would the system lose the capability to handle interrupts immediately?
  4. Recovery: In case the GCLK1 domain is disabled, how does the system recover? Is there an automatic restart mechanism, or would it require manual intervention/reset?
  5. Power Management: Is disabling GCLK1 part of any power management strategy, such as placing the CPU in a low-power state, or preparing the system for shutdown or deep sleep? If so, how are these managed to ensure system stability upon re-enabling the clock?

Understanding these aspects is crucial for our project and system stability. Any insights or additional documentation you could provide would be highly valuable.

Thank you for your assistance.

Best Regards

  • Hi mc b,

    Purpose: What is the intended use case or purpose for disabling the GCLK1 domain? Under what scenarios should this bit be toggled?

    It is mainly helpful in low power modes.

    Impacts: If the GCLK1 domain is disabled by setting this bit, should we expect an immediate halt of the CPU and other critical system functions? What safeguards are implemented to handle such an event?

    No immediate halt will happen.

    Actually, to turn off any clock domain then the corresponding peripherals or cores which are using this clock domain should give "permission" that means they should not use the corresponding domain clock.

    Similarly, as you can see the core should execute the WFI instruction to disable the GCLK1 domain.

    I mean to put the controller in low power mode, we are disabling all the domains and then finally we are disabling GCLK1 and then we are executing the WFI instruction by the core.

    Interrupts: Considering the CPU relies on the GCLK1 domain, if the GCLK1 domain is disabled, how are interrupts affected? Would the system lose the capability to handle interrupts immediately?
    Recovery: In case the GCLK1 domain is disabled, how does the system recover? Is there an automatic restart mechanism, or would it require manual intervention/reset?

    As shared in previous picture, we can configure interrupts to wake the CPU from low power mode.

    For more details refer low power mode example code:

    (+) [FAQ] TMS570LC4357: Examples and Demos available for Hercules Controllers (E.g. TMS570x, RM57x and RM46x etc) - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

    Power Management: Is disabling GCLK1 part of any power management strategy, such as placing the CPU in a low-power state, or preparing the system for shutdown or deep sleep? If so, how are these managed to ensure system stability upon re-enabling the clock?

    I think i covered this in previous answers itself.

    --
    Thanks & regards,
    Jagadish.

  • Thank you very much for your response. It has greatly clarified my query. Additionally, I sincerely appreciate the supplementary information you provided, such as the WFI instruction, which I was considering inquiring about. Your comprehensive and detailed answer is highly valued. Thank you again for your assistance.