Other Parts Discussed in Thread: HALCOGEN
Tool/software:
There seems to be ambiguity in the documentation regarding the GHVSRC register and the Clock Domain Descriptions. Specifically, the ambiguity is related to the clock source configurations and the behavior of HCLK, VCLK, and VCLK2 in sections SPNU563A–March 2.5.1.16 and SPNS195C 6.6.2.1. These are two documents for the TMS570LC4357
Section 2.5.1.16: GHVSRC Register Details:
The GHVSRC register controls the clock source configuration for the GCLK1, HCLK, VCLK, and VCLK2 clock domains. The relevant text states:
Bits 19-16: HVLPM HCLK, VCLK, VCLK2 source on wakeup when GCLK1 is turned off.
Table 2-35: Field Descriptions:
Bit Field Value Description
31-28 Reserved 0 Reads return 0. Writes have no effect. 27-24 GHVWAKE GCLK1, HCLK, VCLK source on wakeup. 19-16 HVLPM HCLK, VCLK, VCLK2 source on wakeup when GCLK1 is turned off.
Section 6.6.2.1: Clock Domain Descriptions:
The documentation here describes the device clock domains and their default clock sources:
Clock Domain - HCLK:
- Divided from GCLK1 through the HCLKCNTL register.
- Allowable clock ratio from 1:1 to 4:1.
- Is disabled through the CDDISx registers bit 1.
Ambiguity Issue:
- GHVSRC SPNU563A Section (2.5.1.16) provides details on how HCLK, VCLK, and VCLK2 sources are managed on wakeup when GCLK1 is turned off. So are they derived from GCM and if the GCLK1 is of derived from another source ?
- SPNS195C Section 6.6.2.1 implies direct derivation from GCLK1, but the integration with GCM is not explicitly mentioned.
Request:
Could you please clarify the following?
- How are the clock sources for HCLK, VCLK, and VCLK2 managed when GCLK1 is turned off?
In this picture it shown as HCLK VLCK AND GCLK connected to GCM , so according to this image GCLK1, HCLK,VCLK derived from GCM but document says HCLK divided from GCLK1 (not GCM)
Clock Domain - HCLK:
- Divided from GCLK1 through the HCLKCNTL register.
Supporting Document References:
- SPNU563A Section 2.5.1.16: GHVSRC Register Details
- SPNS195C Section 6.6.2.1: Clock Domain Descriptions
Your assistance in this matter would be greatly appreciated to ensure accurate and reliable implementation based on the documentation.
Thank you.
Subject: Clarification Needed for GHVSRC Register and Clock Domain Descriptions in TMS570LC4357 Documentation
Description:
There appears to be ambiguity in the documentation regarding the GHVSRC register and the Clock Domain Descriptions for the TMS570LC4357. Specifically, the potential inconsistency is related to the clock source configurations and the behavior of HCLK, VCLK, and VCLK2 in sections SPNU563A 2.5.1.16 and SPNS195C 6.6.2.1.
Section SPNU563A 2.5.1.16: GHVSRC Register Details:
The GHVSRC register controls the clock source configuration for the GCLK1, HCLK, VCLK, and VCLK2 clock domains. The relevant text states:
Bits 19-16: HVLPM HCLK, VCLK, VCLK2 source on wakeup when GCLK1 is turned off.
Table 2-35: Field Descriptions:
Bit Field Value Description
31-28 Reserved 0 Reads return 0. Writes have no effect. 27-24 GHVWAKE GCLK1, HCLK, VCLK source on wakeup. 19-16 HVLPM HCLK, VCLK, VCLK2 source on wakeup when GCLK1 is turned off.
Section SPNS195C 6.6.2.1: Clock Domain Descriptions:
The documentation describes the device clock domains and their default clock sources:
Clock Domain - HCLK:
- Divided from GCLK1 through the HCLKCNTL register.
- Allowable clock ratio from 1:1 to 4:1.
- Is disabled through the CDDISx registers bit 1.
Ambiguity Issue:
The GHVSRC SPNU563A Section (2.5.1.16) provides details on how HCLK, VCLK, and VCLK2 sources are managed on wakeup when GCLK1 is turned off. There is a question regarding whether these sources are derived from the General Clock Module (GCM) or GCLK1, or if they are all derived from the GCM but fall back to another source with GHVSRC settings.
The SPNS195C Section (6.6.2.1) implies that these clock domains are directly derived from GCLK1, but does not explicitly mention their integration with the GCM. If they are derived from GCLK1, it raises a question about their functionality when GCLK1 is off, particularly regarding the usage of GHVSRC -> HVLPM, which selects HCLK, VCLK, and VCLK2 sources on wakeup when GCLK1 is turned off.
Request:
Could you please clarify the following points to resolve the ambiguity?
- How are the clock sources for HCLK, VCLK, and VCLK2 managed when GCLK1 is turned off?
- According to the illustration, it shows HCLK, VCLK, and GCLK connected to the GCM. Is it correct to say that GCLK1, HCLK, and VCLK are derived from the GCM, but the documentation states that HCLK is divided from GCLK1 (not directly from the GCM)?
Supporting Document References:
- SPNU563A Section 2.5.1.16: GHVSRC Register Details
- SPNS195C Section 6.6.2.1: Clock Domain Descriptions
Your assistance in clarifying these points would be greatly appreciated to ensure accurate and reliable implementation based on the documentation.
Thank you for your help.
