AM2432: Crashing writing MSRAM at 0x701FEC00

Eli Mordel

Part Number: AM2432

Tool/software:

Hi,

I'm writing to MSRAM at 0x701FEC00 and crashing to "LDR pc, data_abort_addr" in _vectors:

This MSRAM area was defined as cashed then I also defined as non cached strongly ordered but all cases the program crashes.

The addresses should go up to 0x70280000 so I should have been in a correct MSRAM address area.

What am I missing here ?

Thanks,

Eli

1 month ago

0 Meet Thakar 1 month ago

TI__Expert 5070 points

Hi Eli,

I have taken your inputs and will get back to you as soon as I have an update.

Best Regards,

Meet.

0 Eli Mordel 1 month ago in reply to Meet Thakar

Expert 1245 points

Hi Meet,

I've encountered a similar problem on the DDR . Core-0 writes an integer=1 then Core-1 can read it, but when Core-1 writes it , Core-0 always sees 0.

Both use same DDR address, this area is non-cached or strongly ordered - doesn't matter.

I've defined small byte array instead of int - same results - data written only from Core-0 to Core-1.

Always Core-1 sees Core-0 but not the oposite direction.

Do I have to unlock or define something for multicore use ?

Please help.

Thanks,

Best Regards,

Eli

0 Meet Thakar 29 days ago

TI__Expert 5070 points

Hi Eli,

Eli Mordel said:
I'm writing to MSRAM at 0x701FEC00 and crashing to "LDR pc, data_abort_addr" in _vectors:

Please refer to the memory map layout for AM243: https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/10_01_00_32/exports/docs/api_guide_am243x/MEMORY_MAP.html

Address range from 0x701E0000 to 0x701FFFFF is reserved for DMSC, that's why you are facing the error while accessing this memory.

Eli Mordel said:
I've encountered a similar problem on the DDR . Core-0 writes an integer=1 then Core-1 can read it, but when Core-1 writes it , Core-0 always sees 0.

Could you please elaborate your usecase here and try to explain how you are trying to achieve this? Are you using IPC to synchronize between the cores on whether the write is completing before reading the address from the other core?

Best Regards,

Meet.

+1 Eli Mordel 29 days ago in reply to Meet Thakar

Expert 1245 points

Hi Meet,

I've found my mistake on the DDR case- I declared 32B area instead of 32KB - typo !

Thanks,

Best Regards,

Eli

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AM2432: Crashing writing MSRAM at 0x701FEC00