MSPM0G3507: Latency External ADC Trigger to DMA Complete for Two ADCs - Race ??

Hi Phil,

Please share how you configure your DMA from ADC to SRAM Buffer.

We do have two different ADC memroy map, use the second one might be helpful for your usage:

B.R.

Sal

Hello.

I do not need the memory map.

It is just two DMAs as described above that work fine but I get corrupted data sometimes.

Hi Phil,

And, I assume you are using one GPIO trigger both ADC with EVENT (1:2) channel, correct?

Philip Neaves said:

Sometimes, the data is corrupted in the buffer for ADC1.

What the corrupted data looks like, unvaild value, larger, smaller, less data numbers, or else's case?

Philip Neaves said:

Even at 1 MHz external trigger I get this issue, which seems to be plenty of time for DMA's to finish.

What the sampling time you are using?

I don't think DMA latency makes the data broken. My suspection is that when DMA access data, there is on-going conversion, so that the transmitted data might not be full and corrupted.

Philip Neaves said:

Figure 21-2 says I have no latency from sample start due to ULPCLK use.

Please share the figures you are referring, I don't find this one in latest TRM.

Philip Neaves said:

External trigger rising edge to DMA finish.

We do not have bench test data for this. Maybe you can test it manually.

B.R.

Sal

"My suspection is that when DMA access data, there is on-going conversion, so that the transmitted data might not be full and corrupted."

How can that be ?

The DMA starts on memres0 loaded, therefore ADC conversion complete.

Sample time makes no difference 50ns - 200 ns, still get the issue.

Regards

Phil

Hi Phil,

Misunderstand your cases, I got your point on the DMA transfer. I'll set a demo to test and check.

Sal Ye said:

Philip Neaves said:

Sometimes, the data is corrupted in the buffer for ADC1.

What the corrupted data looks like, unvaild value, larger, smaller, less data numbers, or else's case?

What the corrupted data looks like?

B.R.

Sal

Thanks.

Try 100 ns sample time and external trigger positive edge on a 2:1 splitter.

External trigger is at 1 MHz

8 bit, byte transfer into unsigned char array.

I mean 1:2 splitter...

Hi Philip,

What the corrupted data looks like, unvaild value (larger, smaller) less data numbers, or other case?

B.R.

Sal

Hi...at the moment I am using the ADC in "anger" with real signals.

I really need to input constant voltages into both ADCs to get a proper answer to you.

BUT it "looks like", as you have stated, the data is being DMA's before conversion completed...

A similar issue here...it was a race.....

Hi Philip,

Apologies for too late reply. Here's a demo for reference:
Demo Setup:
- Timer: 32 MHz, triggers two ADC Sampling every 1 µs.
- ADC Data transmission triggered by ADC Memory0 load:
      Transfer size = 1 (8-bit value);
      Stored in a uint_16 buffer (one value per transfer);

- Process repeats 32 times.

adc12_max_freq_dma_8bit_LP_MSPM0G3507_nortos_ticlang.zip

if there is any misunderstanding, pls let me know.

Regards,

Jenney

I hacked Jenney Ni's program to use trigger-next and to use the DMA to transfer the trigger timer (TimG0) CTR register (range [0:31]) rather than the ADC sample.

After a couple of startup wiggles, I saw

1) For ADC0 (DMA CH4): a value of 31 repeatedly

2) For ADC1 (DMA CH3): a value of 21 repeatedly

I slowed the timer trigger cycle to 2us [0:63] and I got the same results, which suggests the CTR wasn't overflowing after the first round.

I re-assigned ADC1 to DMA CH5 (lower priority) and the results were reversed.

Observations:

a) To a first approximation, a DMA transfer seems to take about 10 clocks.

b) A 1us ADC cycle for both ADCs is very close to overrun.

Thanks, that is an elegant experiment.

So with 40 MHz DMA (25 ns)...250 ns X 2= 500 ns
Plus latency for trigger of conversion and sample time....

Surprised it is so long.

Two questions:

1. Why are the both channels different ?

2. If I did a FIFO DMA, will it be effectively quicker per sample since, for example, a single DMA "setup" for say 12 conversions in the FIFO ?

1) The DMA channels have different priorities (ROUNDROBIN=0). By reversing the priorities, I gained some confidence that the ADCs were indeed triggering the DMA simultaneously.

2) The FIFO might be useful, though you would probably have to invert your logic. [Disclaimer: I don't have much experience with the ADC FIFO, but there are some wizards here on the Forum.]

10 clocks was more than I was expecting. But this was also a particular context (and "experimental sample size 1"). I hope to do something similar with maybe the timer soon.

I forgot to mention: I didn't see the symptom you described up at the top of the thread (before I got distracted).