TMS320F280049: SPI STE signal abnormal

Terry Deng said:

More detail show in below waveform, after SPI_B finish translation and STE (yellow color) become low to high, the SPI_A start translation and STE (purple color) become high to low, however SPI_A STE will have an abnormal high pulse in the middle of MOSI (green color), it cause the SPI_A communication error in that frame. May we know if anyone know such issue?

Please explain the clearly. I'm not able to understand the problem you're trying to explain here?

In normally, when SPI_A send data, STE driver to low and should keep low until 16bit MOSI signal finished, then STE turn to high.

However in sometime,  STE do not always keep low in one frame,  it will goto high after 8bit MOSI data, then return to low after one clk, then after remain 8bit MOSI data, STE turn to high. This abnormal frame will cause SPI communication error.

We check many waveform and finally find such SPI_A issue frame usually happen just after SPI_B finish sending (it means the timing that SPI_B STE turn to high).  Although we think the SPI_A and SPI_B should be independence module, it seem SPI_B affect SPI_A STE signal and we cannot understand the reason.

Terry,

I wondering whether this is board artifact. Is this issue seen only on customer board (or) TI board setup? Have you tried reproducing the problem in TI board setup?

Regards,

Manoj

Hi Manoj

we have not tried it in TI board. But we try modify customer code to change STE pin function to GPIO, then operate this signal by GPIO set/clear to replace SPI module STE function, and the issue disappear. So that issue likely SPI module affection but not board artifact.  And look the waveform for SPI STE abnormally pulse, it is very stable for one clock, it do not like a noise but more like a logic signal. so we are suspect if any possible condition will trigger such logic signal from chip internal circuit?

Terry,

Can customer share SPIA / SPIB configuration code? If they can provide their code to re-produce the problem. We can try recreating the problem from our side and then check with design to run simulation to understand the problem.

Also, I hope customer is happy with using SPISTE pin as GPIO pin as workaround?

Regards,

Manoj

Terry Deng said:

More detail show in below waveform, after SPI_B finish translation and STE (yellow color) become low to high, the SPI_A start translation and STE (purple color) become high to low, however SPI_A STE will have an abnormal high pulse in the middle of MOSI (green color), it cause the SPI_A communication error in that frame.

The TMS320F28004x Microcontrollers datasheet (Rev. F) has the following note for the STE pin in master mode:

When the program is using both SPI_A and SPI_B in master mode, perhaps the software timing is changed which means for SPA_A there are no longer back-to-back transfers leading to the STE pin being temporarily de-asserted and then re-asserted.

How many bits are there in each frame?

Gillon

It is 16bit in each frame. May I know more detail for your advice, I am sorry I do not understand clearly what means "back to back transfers" and how affect STE pin? 

Terry,

Can you answer my questions in above post?

Regards,

Manoj

Why is SPIASTE getting pulled high when it enters SPI-B RX interrupt?

Any update?