Hello TI Team,
I am interfacing ENC28J60 ethernet module with TMS320F28379D , but we faced issue in SPI communication , my MOSI pin signal not proper i see on DSO. i have attached my code file , please check and help me where is the issue of spi communication.
Hi Marlyn ,
My SPI pin Signals not getting proper as per timing diagram .my spi configuration is correct or not.
Hi Atul,
I am not able to open up your project due to dependencies but I took a look at the individual files. It looks like your sysconfig file has a different configuration from your board.c file. Looking at the board.c file, this is what I found:
void SPI_init()
{
//mySPI0 initialization
SPI_disableModule(mySPI0_BASE);
SPI_setConfig(mySPI0_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1,
SPI_MODE_MASTER, 8000000, 8);
SPI_enableFIFO(mySPI0_BASE);
SPI_setFIFOInterruptLevel(mySPI0_BASE, SPI_FIFO_TXEMPTY, SPI_FIFO_RXEMPTY);
SPI_disableLoopback(mySPI0_BASE);
SPI_setEmulationMode(mySPI0_BASE, SPI_EMULATION_STOP_AFTER_TRANSMIT);
SPI_enableModule(mySPI0_BASE);
}
Within this you are configuring FIFO but not utilizing it in your empty_sysconfig_main.c file so I would disable FIFO if that is the case. The configuration you have setup is for Master with clock phase of 1 which corresponds to the following timing diagram (from the datasheet). Is this what you are observing?
Lastly, your sysconfig file has the STE polarity as active high, but based on the diagram above it looks like this needs to be active low (normal).
Best Regards,
Marlyn
Hi Marlyn ,
We did this changes , and SPI test ON Saleae Application with logic analyzer .
I am getting following timing diagram.
this miso line is empty .
i want following timing diagram.
