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TMS320F280037C: Is it possible to generate a delay to trip signal at ePWM(or CMPSS)?

Aparna Venugopal
Prodigy 130 points
Part Number: TMS320F280037C

Hi,

I need to have a delay (dead time) at the rising edge of a PWM signal generated from trip signals from CMPSS. Following is the setup:

  • There are two trip outputs from a CMPSS subsystem, TRIP 4 and TRIP 5.
  • I need to create a dead time at the rising edge of the PWM.
  • For that, I can generate a DCAH signal to create a DCAEVT1.sync event to control the rising edge of the PWM.
  • And for the falling edge, I can generate a DCAL signal to create a DCAEVT2.force event to set PWM output to zero.

This looks okay on paper, but would this work practically? I am unable to test this at the moment.

Also, is there more to DCAL and DCAH other than the fact that they are two signals for two different inputs. I was confused because of its name, DCA high and low.

Thanks,

Aparna

  • 0
    TI__Guru 52020 points
    Aparna Venugopal said:
    • For that, I can generate a DCAH signal to create a DCAEVT1.sync event to control the rising edge of the PWM.
    • And for the falling edge, I can generate a DCAL signal to create a DCAEVT2.force event to set PWM output to zero.

    How would you configure your actions? Would you try to set your actions in SW after the sync generates an interrupt?

  • 0 in reply to Nima Eskandari
    Prodigy 130 points

    Hi Nima,

    Thank you for the reply.

    I did not understand your question. All of this would be configured initially.

    In SW, on DCAEVT1.sync, I would set a dead time for rising edge and set CMPA as 0. And the DCAEVT2.force event would pull PWM output to zero and I would get my falling edge.

  • 0 in reply to Nima Eskandari
    Prodigy 130 points

    It has now become clear to me that this particular method wouldn't work for my scenario as I don't want the counter compare register to count up unless the sync event happens. But that is not how it works. It merely resets on a sync event. And the sync event only occurs once every alternate cycle.

    Let me phrase my question in another way now. Is it possible to get a delay from the instance of the digital compare event  to when it reflects in the ePWM signal?

    If not, can the inherent delay in the digital filter be used to configure some delay? I understand it is not the purpose of that component, but can it be used like that?

  • 0 in reply to Aparna Venugopal
    TI__Guru 52020 points
    Aparna Venugopal said:
    Let me phrase my question in another way now. Is it possible to get a delay from the instance of the digital compare event  to when it reflects in the ePWM signal?

    Yes I believe you can do that using the VALLEY CAPTURE block and using the HW/SW DELAY. 

    I think that would do what you want! which is quite fascinating that the HW has support for this without the use of CLB.

  • 0 in reply to Nima Eskandari
    Prodigy 130 points

    Valley capture block will not work in my scenario but found that delayed trip functionality using action qualifier is what I want.