Dear TI engineers,
I did not know clearly about this example from note in C file. I have two questions about this example.
1. According to oscilloscope, I saw epwm1A have high level when CMPA from 3000 to 4000. It seems that epwm1A have 3000 TBCTR delay from 0. Is this right？
2. How to relize action in epwm1B?
Best regard,
coke.
I saw epwm1A have high level when CMPA from 3000 to 4000.
You mean from TBCTR = 3000 to 4000? The EPWM1A will be high till the time it is tripped by GPIO25 using software.
How to relize action in epwm1B?
EPWM1B also using the falling edge of EPWM1B for trip but has an additional delay block using the DCEVTFILT which adds the delay before trip.
Thanks,
Aditya
