TMS320F28379D: Question about SCITXBUF and TXBUF register in SCI module

Hi Green,

Green Deng said:

My customer is very confused about the description of "SCITXBUF" and "TXBUF" registers of SCI module in TRM. ①Are they the same register or two different registers?

Do you know what version of the TRM is being used? I check the current version on the web and don't see any references to "TXBUF" as a register, only SCITXBUF.

Green Deng said:

②Whether SCITXBUF or TXBUF register determines the value of TXRDY?

This is the description in the TRM for TXRDY: "When set, this bit indicates that the transmit data buffer register, SCITXBUF, is ready to receive another character. Writing data to the SCITXBUF automatically clears this bit. When set, this flag asserts a transmitter interrupt request if the interrupt-enable bit, TX INT ENA (SCICTL2.0), is also set. TXRDY is set to 1 by enabling the SW RESET bit (SCICTL1.5) or by a system reset"

Green Deng said:

③When will the value of TXEMPTY be cleared?

The TRM states that "This flag's value indicates the contents of the transmitter's buffer register (SCITXBUF) and shift register (TXSHF)". TXEMPTY will be cleared once there is no content in SCITXBUF or the shift register.

Best Regards,

Marlyn

Hi Marlyn:

Marlyn Rosales Castaneda20 said:

Do you know what version of the TRM is being used? I check the current version on the web and don't see any references to "TXBUF" as a register, only SCITXBUF.

You may find "TXBUF" in TRM at below loctions:

P2275, 19.13.1 SCI FIFO Description: 6. Buffers. ...With the FIFO enabled, TXSHF is directly loaded after an optional delay value (SCIFFCT), TXBUF is not used...

P2277, Notes (1) to the Table 19-4. SCI Interrupt Flags: FIFO mode TXSHF is directly loaded after delay value, TXBUF is not used.

P2297, The description of SCIFFCT.FFTXDLY: In FIFO mode, the buffer (TXBUF) between the shift register and the FIFO should be filled only after the shift register has completed shifting of the last bit. This is required to pass on the delay between transfers to the data stream. In FIFO mode, TXBUF should not be treated as one additional level of buffer. The delayed transmit feature will help to create an auto-flow scheme without RTS/CTS controls as in standard UARTS.

And the lastest loction:

I don't know whether it is appropriate to call "TXBUF" as a "register", but there is such a description in TRM, and the customer is very confused about this description.

Best regards,

Green

Hi Marlyn

Thank you for your answer. But I still don't quite understand the difference between Transmitter−Data Buffer Register(TXBUF, which described in the figura) and transmitter data buffer register (SCITXBUF, which described in TRM as below),

May you please explain the difference between the two in a more vivid way?

Best regards,

Green

Hi Hareesh:

Thanks for your answers. I have no other questions.