• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 208 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049C: TIDM-02002 Why Use ECAP1 For ISR2 Execution?

Kier
Mastermind 8075 points
Part Number: TMS320F280049C
Other Parts Discussed in Thread: TIDM-02002

In the design TIDM-02002:

- ECAP1 is used to trigger ISR2 at 100kHz.

- EPWM5 is used to trigger the SOCs at 100kHz for use by ISR2.

Although they both run at 100kHz, the problem with this is that the relationship between EOC time and reading of the ADCs by ISR2 is arbitrary.

My question please is why is ECAP used at all? Why not trigger SOC AND ISR2 from EPWM5 alone? At least then the ADC conversions for ISR2 have a fixed and possibly controllable relationship with ISR2 execution.

Thank you.

  • 0
    TI__Mastermind 42195 points

    This is due to hardware prioritization of the interrupts. PWM>eCAP>CPU TIMER. This insures that preemption is guaranteed by hardware rather than software. 

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Mastermind 8075 points

    Thanks Cody but I'm not sure why that answers the question. The CPU TIMER is not in the scope of the question and there's no interrupt configured for EPWM5 so why is interrupt priority an explanation please?

  • +1 in reply to Kier
    TI__Mastermind 42195 points

    Kier,

    To answer your questions as directly as possible:

    Kier said:
    My question please is why is ECAP used at all?

    This is because using the eCAP provides interrupt prioritization though hardware.

    Kier said:
    Why not trigger SOC AND ISR2 from EPWM5 alone?

    Because this would not correctly prioritize the interrupts though hardware, and would require software intervention to control preemption of the ISRs.

    Further explanation: As I am sure you are well aware now there are three interrupts used in this code base I have highlighted the triggers for each below. This structure ensures that ISR1 has greater priority than ISR2 and that ISR2 has greater priority than ISR3. This makes the interrupt scheme function to be guaranteed by hardware. I believe this covers your questions above, please let me know if I have missed something.

    #define CLLLC_ISR1_TRIG INT_EPWM1
#define CLLLC_ISR2_TRIG INT_ECAP1
#define CLLLC_ISR3_TRIG INT_ADCC2

    Furthermore, if the intent of your question was to actually to imply the negative question as well. Meaning; to additionally inquire why eCAP1 is not used to also trigger the ADC, then this can be explained by looking at ADCSOCxCTL.TRIGSEL. The options for TrigSEL for the SOCs does not include eCAP1 thus it cannot be used for SOC generation.

    Regards,
    Cody

  • 0 in reply to Cody Watkins
    Mastermind 8075 points

    Hi Cody,

    Many thanks, I understand now. It was the relevance of ISR1 needing a higher priority than ISR2 that I was missing.

    There was no intent to imply that ECAP could be used for SOC trigger but I still wonder why there's no coordination between ADC EOC and ISR2 execution, it just seems to be left to chance.