Hi champs,
The NMI and ITRAP interrupts are not assigned to any PIE Group, does this mean these two vectors are able to generate interrupt even when ST1.INTM is set (global interrupt disabled)?
In CPU interrupt vectors table, we don't assign one core priority to ILLEGAL(ITRAP), does it mean ITRAP is able to generate interrupt when CPU is executing any ISR?
In TRM, we don't have detailed description of CPU Interrupt Logic, is there any information we can refer to so that understand CPU Interrupt Logic better?
Regards,
Luke
