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Original question:

UNIFLASH: TMS320F28388D Run Target After Program Load/Flash Operation did not work

TMS320F28388D: Uniflash 8.1.1 CPU Reset operation does not work for C28X device

Huey Duong
Intellectual 340 points
Part Number: TMS320F28388D
Other Parts Discussed in Thread: UNIFLASH

CPU does not run after loading an image to C28x device using latest uniflash and performing CPU Reset and run action.

To get CPU to run one of the following had to be done:

1. Power cycle CPU

2. Remove computer USB cable connected to FTDI USB. (This effectively removed power from the Isolated side as it is powered by the computer's USB)

So it seems like the software is still holding onto some reset on the JTAG.

This is an issue as my setup is remote. After programming using Uniflash, the product is bricked waiting for someone to power cycle or pull the USB cable. 

I've created a ticket 2 years ago, waiting for a fix.  The bug ticket says it's resolved, but it still does not work for me.

Forum Thread

https://sir.ext.ti.com/jira/browse/EXT_EP-10393

Any suggestions would be helpful.  Thanks.

Using: Windows 11, Uniflash 8.1.1.4146, XDS100v2 USB Debug Probe

[2/1/2023, 10:10:48 AM] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[2/1/2023, 10:10:48 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[2/1/2023, 10:10:49 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[2/1/2023, 10:10:49 AM] [INFO] C28xx_CPU1: GEL Output: CPU2 is out of reset and configured to wait boot. (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
[2/1/2023, 10:10:49 AM] [INFO] C28xx_CPU1: GEL Output: CM is out of reset and configured to wait boot. (If you connected previously, may have to resume CM to reach wait boot loop.)
[2/1/2023, 10:10:49 AM] [INFO] C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after both flash banks are programmed.
[2/1/2023, 10:10:49 AM] [INFO] C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
[2/1/2023, 10:11:14 AM] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[2/1/2023, 10:11:14 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[2/1/2023, 10:11:14 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[2/1/2023, 10:11:15 AM] [INFO] C28xx_CPU1: GEL Output: CPU2 is out of reset and configured to wait boot. (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
[2/1/2023, 10:11:15 AM] [INFO] C28xx_CPU1: GEL Output: CM is out of reset and configured to wait boot. (If you connected previously, may have to resume CM to reach wait boot loop.)
[2/1/2023, 10:11:15 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[2/1/2023, 10:11:15 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[2/1/2023, 10:11:16 AM] [INFO] C28xx_CPU1: GEL Output: CPU2 is out of reset and configured to wait boot. (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
[2/1/2023, 10:11:16 AM] [INFO] C28xx_CPU1: GEL Output: CM is out of reset and configured to wait boot. (If you connected previously, may have to resume CM to reach wait boot loop.)
[2/1/2023, 10:11:16 AM] [INFO] C28xx_CPU1: Writing Flash @ Address 0x00080000 of Length 0x00000002 (page 0)
[2/1/2023, 10:11:16 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[2/1/2023, 10:11:16 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[2/1/2023, 10:11:17 AM] [INFO] C28xx_CPU1: GEL Output: CPU2 is out of reset and configured to wait boot. (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
[2/1/2023, 10:11:17 AM] [INFO] C28xx_CPU1: GEL Output: CM is out of reset and configured to wait boot. (If you connected previously, may have to resume CM to reach wait boot loop.)
[2/1/2023, 10:11:18 AM] [INFO] C28xx_CPU1: PLL configuration status = 1. PLL configured successfully.
[2/1/2023, 10:11:21 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 0
[2/1/2023, 10:11:21 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 1
[2/1/2023, 10:11:22 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 2
[2/1/2023, 10:11:22 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 3
[2/1/2023, 10:11:23 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 4
[2/1/2023, 10:11:24 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 5
[2/1/2023, 10:11:24 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 6
[2/1/2023, 10:11:25 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 7
[2/1/2023, 10:11:26 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 8
[2/1/2023, 10:11:26 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 9
[2/1/2023, 10:11:27 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 10
[2/1/2023, 10:11:27 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 11
[2/1/2023, 10:11:28 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 12
[2/1/2023, 10:11:29 AM] [INFO] C28xx_CPU1: Erasing Flash Bank 0, Sector 13
[2/1/2023, 10:11:29 AM] [INFO] C28xx_CPU1: Data has been buffered at the end of the current data block for 64-bit aligned writes.
[2/1/2023, 10:11:29 AM] [INFO] C28xx_CPU1: Writing Flash @ Address 0x00088104 of Length 0x00001ba4 (page 0)
[2/1/2023, 10:11:35 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x00088104 of Length 0x00001BA4
[2/1/2023, 10:11:35 AM] [INFO] C28xx_CPU1: Writing Flash @ Address 0x00089ca8 of Length 0x00000048 (page 0)
[2/1/2023, 10:11:37 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x00089CA8 of Length 0x00000048
[2/1/2023, 10:11:37 AM] [INFO] C28xx_CPU1: Writing Flash @ Address 0x00089cf0 of Length 0x000048d8 (page 0)
[2/1/2023, 10:11:42 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x00089CF0 of Length 0x00002000
[2/1/2023, 10:11:47 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x0008BCF0 of Length 0x00002000
[2/1/2023, 10:11:48 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x0008DCF0 of Length 0x000008D8
[2/1/2023, 10:11:48 AM] [INFO] C28xx_CPU1: Writing Flash @ Address 0x0008e5c8 of Length 0x000002f8 (page 0)
[2/1/2023, 10:11:50 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x0008E5C8 of Length 0x000002F8
[2/1/2023, 10:11:50 AM] [INFO] C28xx_CPU1: Writing Flash @ Address 0x00098000 of Length 0x00007ff0 (page 0)
[2/1/2023, 10:11:55 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x00098000 of Length 0x00002000
[2/1/2023, 10:12:00 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x0009A000 of Length 0x00002000
[2/1/2023, 10:12:04 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x0009C000 of Length 0x00002000
[2/1/2023, 10:12:09 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x0009E000 of Length 0x00001FF0
[2/1/2023, 10:12:09 AM] [INFO] C28xx_CPU1: Writing Flash @ Address 0x0009fff0 of Length 0x00005346 (page 0)
[2/1/2023, 10:12:09 AM] [INFO] C28xx_CPU1: Data has been buffered at the end of the current data block for 64-bit aligned writes.
[2/1/2023, 10:12:14 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x0009FFF0 of Length 0x00002000
[2/1/2023, 10:12:19 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x000A1FF0 of Length 0x00002000
[2/1/2023, 10:12:22 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x000A3FF0 of Length 0x00001344
[2/1/2023, 10:12:22 AM] [INFO] C28xx_CPU1: Writing buffered data @ Address 0x00080000 of Length 0x00000004
[2/1/2023, 10:12:23 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x00080000 of Length 0x00000004
[2/1/2023, 10:12:23 AM] [INFO] C28xx_CPU1: Writing buffered data @ Address 0x000A5334 of Length 0x00000004
[2/1/2023, 10:12:24 AM] [INFO] C28xx_CPU1: --Verifying Flash @ Address 0x000A5334 of Length 0x00000004
[2/1/2023, 10:12:26 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[2/1/2023, 10:12:27 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[2/1/2023, 10:12:27 AM] [INFO] C28xx_CPU1: GEL Output: CPU2 is out of reset and configured to wait boot. (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
[2/1/2023, 10:12:27 AM] [INFO] C28xx_CPU1: GEL Output: CM is out of reset and configured to wait boot. (If you connected previously, may have to resume CM to reach wait boot loop.)
[2/1/2023, 10:12:27 AM] [SUCCESS] Program Load completed successfully.

Also.  Clicking the CPU Reset "Reset Now" button more than once produces an error and does nothing to the CPU.

[2/1/2023, 10:08:28 AM] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[2/1/2023, 10:08:28 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[2/1/2023, 10:08:29 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[2/1/2023, 10:08:29 AM] [INFO] C28xx_CPU1: GEL Output: CPU2 is out of reset and configured to wait boot. (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
[2/1/2023, 10:08:29 AM] [INFO] C28xx_CPU1: GEL Output: CM is out of reset and configured to wait boot. (If you connected previously, may have to resume CM to reach wait boot loop.)
[2/1/2023, 10:08:41 AM] [INFO] Executing Reset: CPU Reset
[2/1/2023, 10:08:42 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
[2/1/2023, 10:08:42 AM] [INFO] C28xx_CPU1: GEL Output: Memory Map Initialization Complete
[2/1/2023, 10:08:42 AM] [ERROR] C28xx_CPU1: Failed Software Reset: A reset is already in progress
[2/1/2023, 10:08:42 AM] [INFO] C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
[2/1/2023, 10:08:43 AM] [INFO] C28xx_CPU1: GEL Output: CPU2 is out of reset and configured to wait boot. (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
[2/1/2023, 10:08:43 AM] [INFO] C28xx_CPU1: GEL Output: CM is out of reset and configured to wait boot. (If you connected previously, may have to resume CM to reach wait boot loop.)

  • 0
    TI__Guru* 87105 points

    Hi Huey Duong,

    I am assigning this to the tools team.  They will get back to you this week.

    Thanks and regards,
    Vamsi

  • +1
    TI__Guru**** 450961 points
    Huey Duong said:

    I've created a ticket 2 years ago, waiting for a fix.  The bug ticket says it's resolved, but it still does not work for me.

    Forum Thread

    https://sir.ext.ti.com/jira/browse/EXT_EP-10393

    The issue in the above ticket is for the target not running after program flash. I can confirm that this is resolved in UniFlash 8.1.1 using F2838xD. If I flash the program, the program will run successfuly afterwards.

    The extra thing you are doing is CPU reset after the program load. If I do that also, then I need to power cycle like you mentioned to get it to run correctly again.

    When I flash with CCS 12.2.0 and then do a CPU reset, I need to restart the program get it to run correctly again. 

    Hence I'm not sure if the is an actual UniFlash bug. I will need to have the C2000 experts comment further

  • 0 in reply to Ki
    TI__Guru* 87105 points

    Hi Huey Duong,

    We will review and get back to you early next week.

    Thanks and regards,

    Vamsi

  • 0 in reply to Ki
    Intellectual 340 points

    Thanks for testing this Ki. You are correct and the cpu does indeed start up if I remove the "reset CPU" option.

  • 0 in reply to Ki
    Intellectual 340 points

    That being said, there is still something not quite right with the "reset cpu" feature.

    2 things I've observed:

    1.  In uniflash, as mentioned before, the "reset cpu" does not seem to work. 

    2. After programming with uniflash and having CPU running, our program accepts a CLI command to reset cpu which executes "SysCtl_simulateReset(SYSCTL_CAUSE_CPU1RSN)".  This also seems to just halt the CPU.  Does not do a reset.

    After power cycling, the CLI reset command works fine.

    #2's behaviour is similar to what happens when using CCS and using the debug feature.

    The original issue is resolved, not sure if you want me to create a new ticket for CPU reset.

    Thanks

  • 0 in reply to Huey Duong
    TI__Guru**** 450961 points
    Huey Duong said:
    not sure if you want me to create a new ticket for CPU reset.

    Yes please! That would be much appreciated. I will close this thread.