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TMS320F28384S: Connectivity manager questions

NY
Expert 3040 points
Part Number: TMS320F28384S 
1) Regarding the TMS320F28384S, what are the precautions when using CM (Connectivity Manager)? Is it necessary to create a project that is different from the DSP side (C28 CPU)?

2) I would like to know the points to note when creating a memory map and appropriate allocation when the CM (connectivity manager) and DSP side (C28 CPU) coexist. I would like to know RAM and flash separately.

3) Is it possible to run the program only on the DSP side (C28 CPU)? Conversely, what should I do on CCS when debugging both CM and CPU?

4) I would like to know how CM and CPU memory are shared. Is it possible to share a global variable and make it behave like accessing it at the same time? "In that case, what would be a specific description example?"

5)  I saw a description that CM always needs reset release from CPU. Does this mean that there is no choice but to start booting from the real CPU? Also, if you want to consider the FW update mechanism, is it impossible to implement a method such as stopping the CPU from the CM and updating the CPU side?

  • 0
    TI__Guru 50430 points

    Hi,

    Please refer to datasheet for memory for CM and C28x memory ranges.

    Please refer to this link for debugging CM and C28x concurrently.

    https://software-dl.ti.com/ccs/esd/documents/ccs_multi-core-debug.html

    Regards, Santosh

  • 0
    TI__Guru* 93915 points
    NY said:
    2) I would like to know the points to note when creating a memory map and appropriate allocation when the CM (connectivity manager) and DSP side (C28 CPU) coexist. I would like to know RAM and flash separately.

    Each processor has its own dedicated memory (and hence a memory map). There is also message RAM to share data between the three CPUs. Please see the memory maps in page 246 of the datasheet.

    NY said:
    3) Is it possible to run the program only on the DSP side (C28 CPU)? Conversely, what should I do on CCS when debugging both CM and CPU?

    Yes, it is possible to run the program solely on any one of the three CPUs. I didn't understand the 2nd question. Through CCS, you will indeed be able to connect to any one of the 3 CPUs (5 CPUs , if you count the CLAs as well).

    NY said:
    5)  I saw a description that CM always needs reset release from CPU. Does this mean that there is no choice but to start booting from the real CPU?

    Your understanding is correct. By "real CPU", I presume you are referring to CPU1. CPU1 has to release CM from reset. CPU1 is always the first CPU to "boot up".

    NY said:
    Also, if you want to consider the FW update mechanism, is it impossible to implement a method such as stopping the CPU from the CM and updating the CPU side?

    Are you asking if it is possible to stop CPU1 from CM in order to perform a firmware update for CPU1?

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 3040 points 
    Hi Hareesh-san, thank you so much fory our answer above, but please answer for #4 as well. 

    4)     I would like to know how CM and CPU memory are shared. Is it possible to share a global variable and make it behave like accessing it at the same time? "In that case, what would be a specific description example?"

    For your question, 

    Are you asking if it is possible to stop CPU1 from CM in order to perform a firmware update for CPU1?

    Yes, customer want to know If you stop CPU1 from CM to update CPU1, the reset release signal will not be supplied, so CM will not work, or once CM is started, it is possible to operate without receiving the reset release signal from CPU1.

  • 0 in reply to NY
    TI__Guru* 93915 points
    NY said:
    Yes, customer want to know If you stop CPU1 from CM to update CPU1, the reset release signal will not be supplied, so CM will not work, or once CM is started, it is possible to operate without receiving the reset release signal from CPU1.

    I regret I don’t understand exactly what the customer requirement is. When the firmware update is being done for CPU1, what are CPU2 and M4 expected to be doing?

    Q4 will be answered by someone in the software team.

  • 0 in reply to NY
    TI__Expert 6105 points

    Hi NY,

    For customer, here is a bit further clarification on the question (taken from SPRABV4 application note):

    From the host side, step 6 indicates that the loading and programming of CPU1 and CM actions are initially taken in one step before the host programmer closes. If they are asking that once CPU1 and CM are first programmed, and control is given to CM, if the host programmer is executed again, then control will be given to CPU1 when performing a firmware update (DFU). 

    Thanks,

    Charles