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TMS320F28377D: GPIO muxing in dual core DSP and GPIO logic in TMR

UserHomeInit
Expert 2145 points
Part Number: TMS320F28377D
Other Parts Discussed in Thread: TMS320F28379D

Dear TI hello,

I am currently working on developing a new GPIO driver for the TMS320F28379D. However, I have some questions regarding the documentation.

In the GPIO Logic for Single Pin 8.1 diagram, I couldn't find clear explanations for "Peripheral A," "Peripheral B," and so on. The functional block lacks proper grouping, and each peripheral is named individually.

I am aware that multiple peripherals can be connected to any GPIO, but the information in the TMR documentation is not sufficiently clear, and I couldn't find the definition of peripharle A B C.

The second point of concern is the GPIO index in the GPIO Muxed Pins 7-2 table. I am unsure if it is a hardware-related aspect or if it pertains to the GPIO TI function responsible for configuring the GPIO.

I am attempting to comprehend the combinations listed in the GPIO Logic for a single pin, but I find it challenging to distinguish between GPyGMUX and GPyMUX as they seem to be interconnected.

Thank you in advance,

S.Tarik  

  • 0
    TI__Mastermind 30185 points

    Hello Tarik,

    UserHomeInit said:
    In the GPIO Logic for Single Pin 8.1 diagram, I couldn't find clear explanations for "Peripheral A," "Peripheral B," and so on. The functional block lacks proper grouping, and each peripheral is named individually.

    This is left generic on purpose, because not every device's GPIO configurations are the same as far as what peripherals they can connect to. You can refer to section 8.7 GPIO and Peripheral Muxing for information on what peripherals can be connected to what GPIO pins.

    UserHomeInit said:
    The second point of concern is the GPIO index in the GPIO Muxed Pins 7-2 table. I am unsure if it is a hardware-related aspect or if it pertains to the GPIO TI function responsible for configuring the GPIO.

    It is the user's responsibility to configure the GPIO registers GPyGMUXn and GPyMUXn for their intended use/application of the GPIO pin; all pins are by default configured as just GPIO.

    UserHomeInit said:
    I am attempting to comprehend the combinations listed in the GPIO Logic for a single pin, but I find it challenging to distinguish between GPyGMUX and GPyMUX as they seem to be interconnected.

    You can refer to the registers section of the GPIO chapter for register questions. GPyGMUXn is the mux selection for the peripheral group, and GPyMUXn is the mux selection for the mux register. Both must be configured appropriately, as shown in the GPIO Muxed Pins table you have in the screenshot. For example, to use GPIO7 for eQEP3B, you would set the GPAGMUX1 GPIO7 bits to be 01b and GPAMUX1 GPIO7 bits to be 01b. You can look at table 8-12 GPIO_CTRL_REGS Registers to see what mux registers control which GPIO pins.

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    Expert 2145 points

    Hello Omer,

    UserHomeInit said:
    The second point of concern is the GPIO index in the GPIO Muxed Pins 7-2 table. I am unsure if it is a hardware-related aspect or if it pertains to the GPIO TI function responsible for configuring the GPIO.

    Thank you for you answer,  I'd like to inquire further about the index and its specific applications. Can you clarify on how this information is utilized?

  • 0 in reply to UserHomeInit
    TI__Mastermind 30185 points

    Hello Tarik,

    I'm not sure what you mean, can you please clarify your question? The table provides bit values that configure the GPIO register to be used by a specific peripheral, so if you want to change a GPIO from just acting as a GPIO you need to modify the specified GPIO mux registers. The choice of what to change it to is up to you, but once you decide you can change the registers using your program and utilizing driverlib.

    Best regards,

    Omer Amir