TMS320F28P650DK: CPU2 and CPU1 issue

Hi,

Irene Boben said:

1. When I disconnect CPU2 in CCS, CPU1 also gets disconnected. Why is this? This was not the behavior with other multicore processor like F28379D

Let me check on this and get back to you.

Irene Boben said:

Now I connect CPU1 and CPU2 code stops working (LED2 not blinking). Is this expected? Or is there a sequence that has to be followed/

This is because when you connect CPU1, CPU1 Gel file issues a reset which resets both CPU hence both LED stops blinking. 

Regards,

Vivek Singh

Hi Vivek,

My question was not clear before. 

So I have , in CPU2 boot from flash LED blinking code running.

Now I load something in CPU1. This puts CPU2 into a bad state. It is stuck at '_system_post_cinit()'

Every time I load something in CPU1 , the CPU2 code does not work and I have to reload the CPU2 code to make it work.

Also,

I have chosen bank3 and bank 4 for  CPU2 by setting DevCfgRegs.BANKMUXSEL.all = 0x000003C0U;

In the CCXML, in flash setting, I have done the same bank setting.

When I choose CPU2 boot mode as 0x83, I am unable to load program in CPU1 or CPU2.

I get the following error: 

C28xx_CPU1: Flash Programmer: Error erasing Bank 3 FMSTAT (STATCMD on some devices) value = 65. Operation Cancelled (0).
C28xx_CPU1: File Loader: Memory write failed: Unknown error
C28xx_CPU1: GEL: File: ~...\CPU1_GPIO.out: Load failed.

1. Why does this error come?

2. What is the significance of selecting bank in CCXML?

3. Do I need to do anything extra if I want BANK3 and BANK4 for CPU2 and BANK 0 to 2 for CPU1?

4. Why is setting bootmode to 0x83 causing load error for both CPU1 and CPU2?

Yes, it's because when you load code on CPU1, it's Gel file issues a reset and CPU1 reset, resets CPU2 as well because CPU1 is main controller on this device. After loading code on CPU1, you don't have to load code on CPU2. You just need to click on restart and that should work. 

Let me loop in our flash expert to reply on this.

Hi Irene,

This is assigned to me today.  I will review and get back to you in a day or two.  Thank you.

Regards,
Vamsi

Hi Irene,

Before doing any flash operations using the F28P65x flash plugin,

(a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI (CCS debug view -> Tools -> On-Chip Flash).

(b) Please select the flash banks that you would like the flash plugin to erase (select separately in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI). 

(c) Please configure the PLL using the Configure Clock button in CPU1 flash plugin GUI before doing any CPU2 flash plugin operations (including loading any executable to CPU2 flash).

(d) If you want CCS to remember the settings that you configure in the flash plugin GUI, you need to click on the "Remember My Settings" button at the bottom of the GUI.  This will make the plugin to remember your configured settings for the next iteration.

Let me know how it goes.

Thanks and regards,

Vamsi

Hi Vamsi,

I configured the  On-Chip Flash. Bank 0-2 is assigned for CPU1 and Bank 3 and 4 to CPU2. In CPU1 I am doing a similar setting by configuring the  DevCfgRegs.BANKMUXSEL register. I am still facing the below issues.

1. If boot mode for CPU2 is  0x83, I am unable to load program in CPU1 or CPU2.

I get the following error although BANK 2 is assigned to CPU1.

C28xx_CPU1: Flash Programmer: Error erasing Bank 2 FMSTAT (STATCMD on some devices) value = 65. Operation Cancelled (0).
C28xx_CPU1: File Loader: Memory write failed: Unknown error
C28xx_CPU1: GEL: File: C:\Users\iboben\OneDrive - MathWorks\Irene\Embedded Targets\24a\P65x\Bugs\CPU1_GPIO.out: Load failed.

2. If boot mode for CPU2 is  0x03, the code is running when I do CPU1 first and then CPU2. However, the moment I load a new code in CPU1, CPU2 goes into a bad state. It is stuck at '_system_post_cinit()'

I have to reload CPU2 code every time I load something in CPU1.

3. Also this question remains: When I disconnect CPU2 in CCS, CPU1 also gets disconnected. Why is this? This was not the behavior with other multicore processor like F28379D

Looking forward to your response.

Thanks and regards,

Irene

Hi Irene,

1) What do you mean by bootmode for CPU2 is 0x83?  Where and how did you configure this?  

2) Which version of CCS are you using?

3) Are you trying to load both CPU1 and CPU2 images using CPU1?  Or Are you loading CPU1 image from CPU1 and CPU2 image from CPU2?

4) What are the values you configured for CMDWEPROTx registers in the flash plugin GUI?

Thanks and regards,

Vamsi

Hi Vamsi,

Please find my answers in-line.

1) What do you mean by bootmode for CPU2 is 0x83?  Where and how did you configure this?  -> In the CPU1 flash init code, I am setting boot mode for CPU2 by running following line of code:

mode |= (uint32_t)((uint32_t)0x5A << 24);
mode |= 0x83; // Flash boot option 4

// CPU01 To CPU02 IPC Command Register

IPC_setBootMode(IPC_CPU1_L_CPU2_R, mode);

// CPU01 to CPU02 IPC flag register

IPC_setFlagLtoR(IPC_CPU1_L_CPU2_R, (IPC_FLAG0 | IPC_FLAG31));

2) Which version of CCS are you using? CCS 12.4.0

3) Are you trying to load both CPU1 and CPU2 images using CPU1?  Or Are you loading CPU1 image from CPU1 and CPU2 image from CPU2?

I am loading CPU1 image from CPU1 and CPU2 image from CPU2

4) What are the values you configured for CMDWEPROTx registers in the flash plugin GUI?

I have not modified this.

Thanks and regards,

Irene

Hi Irene,

1) Can you send the CPU1 flash plugin GUI snapshot showing the CPU to bank mapping configuration that you selected?

2) Can you send the CPU1 and CPU2 flash plugin snapshots showing the flash bank selection that you configured for the flash plugin to erase?

Thanks and regards,

Vamsi

Hi Vamsi,

CPU1 flash plugin GUI:

CPU2 flash plugin GUI:

Hope this helps.

Thanks and regards,

Irene

Vivek Singh said:

Irene Boben said:

1. When I disconnect CPU2 in CCS, CPU1 also gets disconnected. Why is this? This was not the behavior with other multicore processor like F28379D

Let me check on this and get back to you.

Hi Irene,

Just wanted to update you on this specific issue. We acknowledge that this is how it work today. This is happening due to one of the feature which got implement in recent CCS release. We have filed this issue with our CCS support team and they will look at it in detail and see if this can be fixed but that would take some time.

Thank you for providing this feedback. We appreciate it.

Regards,

Vivek Singh

Hi Irene,

Can you provide us some executable files to be able to reproduce this issue on our side?

Thanks and regards,

Vamsi

executables.zip

Hi Vamsi,

I have attached the executables. I am not sure which setting I am missing out here. The moment I reload CPU1 flash, the code running in CPU2 flash stops.

Thanks and regards,

Irene

Hi Vivek,

Could you share the tracking details ,if present , so that I can know when its fixed.

Thanks and regards,

Irene

Hi Irene,

Thank you.  I will try the executable and get back to you by the end of the week.

Thanks and regards,
Vamsi

Thank you Vamsi

Hi Vamsi,

I did do it that way. But I will give it a try again. Meanwhile when you successfully load both CPUs are two LEDs blinking. And then load CPU1 again, does the CPU2 code work? I mean are both LEDs still blinking?

Thanks and regards,

Irene

Hi Irene,

I did not check the execution behavior.  I can help with programming - and I did not see any issue programming.

Let me know how it goes after you try the settings that I suggested.

Please note: I am out of office currently and will be back next week.  

Thanks and regards,

Vamsi

HI Vamsi,

By making the changes in the On Chip flash settings. I was able to load both the CPUs properly.

The issue that CPU2 stops working when I reload CPU1 was because of the MCUCNFx registers. I added SysCtl_emulateDevice in my code and it worked fine. This is something new that I see from its predecessors F2838x and F2837xD

Do we have any documentation that details these new changes wrt to F28P65x processor?

Thanks and regards,

Irene

Hi Irene,

Glad the suggested flash plugin settings helped to load the images in both CPU's banks successfully.

Regarding the MCUCNFx: Are these registers not documented in the TRM?  If this is missing in the migration guide, I can suggest to our documentation team.  Please let me know.

Thanks and regards,
Vamsi 

Hi Vamsi,

Yes this is missing in the migration guide. This is needed since this is a new register and without it properly configured CPU2 stops working on reloading CPU1

Thanks and regards,

Irene