Other Parts Discussed in Thread: C2000WARE
We have a power electronics control appllication and we want the whole code to load from Flash and run from RAM for 2 reasons:
- ISR performane without any Flash wait states
- Main() code writes to the same flash bank that stores the code, so ISR should run uninterrupted while main() is doing flash operations (no read stalls)
But I am aware that boot code (like boot28.asm) needs to be run from Flash only as it does the work of loading to RAM. So, at least some part of the RTS library needs to be run directly from Flash.
I am using the cmd as below text and also I have converted the whole project code to ramfunc using --ramfunc in Runtime model options. In linker , we use COFF, so #if defined(__TI_EABI__) parts can be ignored. The flash to RAM load is done using BINIT. In f28004x_codestartbranch.asm, only watchdog is being disabled before long branching to _c_int00
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x086000, length = 0x000002
RAMGS0_3 : origin = 0x00C000, length = 0x007FF8
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* BANK 0 */
FLASH_BANK0_SEC6_15 : origin = 0x086002, length = 0x009FFE /* on-chip Flash */
// FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */
// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */
RAMM0_1 : origin = 0x0000F4, length = 0x000704 /* on-chip RAM block M0 and M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMLS0_7 : origin = 0x008000, length = 0x004000
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
.cinit : > FLASH_BANK0_SEC6_15, PAGE = 0, ALIGN(4)
.binit : > FLASH_BANK0_SEC6_15, PAGE = 0, ALIGN(4)
.text : LOAD > FLASH_BANK0_SEC6_15,
RUN > RAMGS0_3
PAGE = 0, ALIGN(4), table(BINIT)
codestart : > BEGIN PAGE = 0, ALIGN(4)
copysections : > FLASH_BANK0_SEC6_15, PAGE = 0, ALIGN(4) /* Used by file SectionCopy_nonBIOS.asm */
.stack : > RAMM0_1 PAGE = 1
.switch : LOAD > FLASH_BANK0_SEC6_15,
RUN > RAMGS0_3
PAGE = 0, ALIGN(4), table(BINIT)
#if defined(__TI_EABI__)
.init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS5, PAGE = 1
.bss:cio : > RAMLS5, PAGE = 1
.data : > RAMLS6, PAGE = 1
.sysmem : > RAMLS6, PAGE = 1
.const : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
#else
.pinit : > FLASH_BANK0_SEC6_15, PAGE = 0, ALIGN(4)
.ebss : > RAMLS0_7, PAGE = 1
.esysmem : > RAMLS0_7, PAGE = 1
.cio : > RAMLS0_7, PAGE = 1
.econst : LOAD > FLASH_BANK0_SEC6_15,
RUN > RAMGS0_3
PAGE = 0, ALIGN(4), table(BINIT)
#endif
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
#if defined(__TI_EABI__)
/* CLA specific sections */
Cla1Prog : LOAD = FLASH_BANK0_SEC4,
RUN = RAMLS0,
LOAD_START(Cla1ProgLoadStart),
RUN_START(Cla1ProgRunStart),
LOAD_SIZE(Cla1ProgLoadSize),
PAGE = 0, ALIGN(4)
#else
/* CLA specific sections */
Cla1Prog : LOAD > FLASH_BANK0_SEC6_15,
RUN > RAMGS0_3
PAGE = 0, ALIGN(4), table(BINIT)
#endif
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
#if defined(__TI_EABI__)
.TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
RUN = RAMLS4
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
.TI.ramfunc : LOAD > FLASH_BANK0_SEC6_15,
RUN > RAMGS0_3
PAGE = 0, ALIGN(4), table(BINIT)
#endif
RTS_TEXT_FLASH : > FLASH_BANK0_SEC6_15,
PAGE = 0, ALIGN(4)
{
rts2800_fpu32.lib<boot28.asm.obj> (.text)
rts2800_fpu32.lib<exit.c.obj> (.text)
rts2800_fpu32.lib<cpy_tbl.c.obj> (.text)
rts2800_fpu32.lib<args_main.c.obj> (.text)
rts2800_fpu32.lib<pre_init.c.obj> (.text)
rts2800_fpu32.lib<startup.c.obj> (.text)
rts2800_fpu32.lib<memcpy.c.obj> (.text)
}
RTS_TEXT_RAM : LOAD > FLASH_BANK0_SEC6_15,
RUN > RAMGS0_3
PAGE = 0, ALIGN(4), table(BINIT)
{
--library=rts2800_fpu32.lib(.text)
}
.scratchpad : > RAMLS0_7, PAGE = 1
//.bss_cla : > RAMLS0_7, PAGE = 1
//Cla1DataRam : > RAMLS2, PAGE = 1
//cla_shared : > RAMLS1, PAGE = 1
#if defined(__TI_EABI__)
.const_cla : LOAD = FLASH_BANK0_SEC2,
RUN = RAMLS3,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
PAGE = 0, ALIGN(4)
#else
.const_cla : LOAD > FLASH_BANK0_SEC6_15,
RUN > RAMGS0_3
PAGE = 0, ALIGN(4), table(BINIT)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
We are facing 2 issues:
- How do we ensure that only boot code is running directly from Flash while all other code can be run from RAM? I tried to run memcpy.c.obj from RAM, but then microcontroller fails to boot. The currect working memory allocation is shown in photo below. For our purpose memcpy should be running from RAM as we might need to use it in ISR. This is just one example. Ideally only boot.asm should be running directly from Flash.
- With current settings, we cannot debug the code. Debug runs normally when we use a different linker where we load and run code from RAM only.
