TMS320F28P659DK-Q1: ePWM unexpected behavior when TBCTR is counting down

Davide Dentoni

Part Number: TMS320F28P659DK-Q1
Other Parts Discussed in Thread: C2000WARE

Hello support,
I'm reporting you an unexpected behavior of ePWM.

Setup:
SYSCLK = 200MHz
EPWMCLK = 200MHz (PERCLKDIVSEL.EPWMCLKDIV = 0)

setup pf ePWM1 and ePWM3
both configured in UP-DOWN mode
both configured with CLKDIV = 0 and HSPCLKDIV = 1 (total prescaler = 2) so that TBCLK = 100MHz
ePWM1 (AQCTLA) is configured to generate output A: HIGH on CMPA when counting UP, LOW on CMPB when counting UP
ePWM3 (AQCTLA) is configured to generate output A: HIGH on CMPA when counting DOWN, LOW on CMPB when counting DOWN
ePWMs are synced (ePWM1 provides the sync to ePWM3) and ePWM3 PRD reload is linked to ePWM1 (through EPWMXLINK.TBPRDLINK)

Here the issue:
ePWM1_A is generated as expected
on ePWM3_A is not generated, even if TBCTR is running and CMPA/CMPB/TBPRD hold the right values.

If I change (even in runtime during debug session) the value of ePWM3 HSPCLKDIV to ZERO, the ePWM3_A is generated (of course
with a frequency double as desired).

On the other hand, keeping CLKDIV = 0 and HSPCLKDIV = 1, if I change the AQCTLA configuration of ePWM3 as follows
HIGH on CMPA when counting UP, LOW on CMPB when counting UP
the signal ePWM3_A is generated.

Finally, if I set
- EPWMCLK = 100MHz (PERCLKDIVSEL.EPWMCLKDIV = 1),
- ePWM1/ePWM3 with CLKDIV = 0 and HSPCLKDIV = 0 (total prescaler = 1) so that TBCLK = 100MHz,
- ePWM1 (AQCTLA) configured to generate output A: HIGH on CMPA when counting UP, LOW on CMPB when counting UP
- ePWM3 (AQCTLA) configured to generate output A: HIGH on CMPA when counting DOWN, LOW on CMPB when counting DOWN
everithing works fine --> ePWM3_A is generated properly

It seems that there is a sort of incompatibility between
- setting of TBCLK different than EPWMCLK, and
- the behavior of ePWM when it is counting down.

Do you have any idea?
Maybe something could be missing is my configuration ?

over 1 year ago

0 Prarthan Bhatt over 1 year ago

TI__Genius 9635 points

Davide Dentoni said:
ePWM1_A is generated as expected
on ePWM3_A is not generated, even if TBCTR is running and CMPA/CMPB/TBPRD hold the right values.

What are the CMPA CMPB values and when EPWM1 TBPRD is loaded what value is written to it ? Are both modules in same mode (up-down count )?

Davide Dentoni said:
On the other hand, keeping CLKDIV = 0 and HSPCLKDIV = 1, if I change the AQCTLA configuration of ePWM3 as follows
HIGH on CMPA when counting UP, LOW on CMPB when counting UP
the signal ePWM3_A is generated

The fact that it works on LOW on CMPB counting up and HIGH on CMPA counting up, I suspect its missing action qualifier event on PRD load.

Can you share waveform of the same depicting and if possible share the code so I can try to replicate ?

Thanks.

0 Davide Dentoni over 1 year ago in reply to Prarthan Bhatt

Prodigy 175 points

Hello,
here my answers

"What are the CMPA CMPB values and when EPWM1 TBPRD is loaded what value is written to it ? Are both modules in same mode (up-down count )?"

ePWM1.CMPA = 0x000A0000
ePWM1.CMPB = 0x009C0000

ePWM3.CMPA = 0x009C0000
ePWM3.CMPB = 0x000A0000

ePWM1.TBPRD = ePWM3.TBPRD = 0x00A6
ePWM1.TBPRDHR = ePWM3.TBPRDHR = 0x0000

Both module are configured in UP-DOWN count mode.

"The fact that it works on LOW on CMPB counting up and HIGH on CMPA counting up, I suspect its missing action qualifier event on PRD load."
What do you mean ? In which register can I comfigure an action qualifier event on PRD load ?

"Can you share waveform of the same depicting and if possible share the code so I can try to replicate ?"
Following file LLC_Extract.c contains the function used to configure both PWM.
Function is called twice, each time with different arguments

To configure ePWM1 you can call the function with PeriodCountReload = 0xA6, Position = FB_H1L2_BRIDGE
To configure ePWM3 you can call the function with PeriodCountReload = 0xA6, Position = FB_H2L1_BRIDGE

No matter about the value of FB_H1L2_BRIDGE and FB_H2L1_BRIDGE, anyway in my project are:
FB_H1L2_BRIDGE = 1
FB_H2L1_BRIDGE = 2

Pay attention that, in order to have my setup, you must set
SYSCLK = 200MHz
EPWMCLK = 200MHz (PERCLKDIVSEL.EPWMCLKDIV = 0)

LLC_Extract.c

static void ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet(uint32_t BaseAddress, uint16_t PeriodCountReload, LLCBRIDGE_Position_t Position)
{

    uint32_t pwmPeriod_ticks;


	/*
	 * compute PERIOD reload value to be loaded in HR registers
	 */
	pwmPeriod_ticks = (uint32_t)((float32_t)PeriodCountReload * 65536.0f);/* polyspace MISRA2012:10.8 [Justified:Low] "cast needed by application" */



    /*
	 * Direct access to HR PERIOD register
	 * should be faster than using drivers
	 */
    HRPWM_setTimeBasePeriod(BaseAddress, pwmPeriod_ticks);


    HRPWM_setTimeBaseCounter(BaseAddress, 0);
    HRPWM_setPhaseShift(BaseAddress, 0);
    HRPWM_setTimeBaseCounterMode(BaseAddress, EPWM_COUNTER_MODE_UP_DOWN);
    HRPWM_setEmulationMode(BaseAddress, EPWM_EMULATION_FREE_RUN);
	
	/**< Set the dividers in order to match the value of EPWMCLK_LLC **/
	HRPWM_setClockPrescaler(BaseAddress, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2);



	/**< Loads TBPRD on PERIOD **/
    HRPWM_setPeriodLoadMode(BaseAddress, EPWM_PERIOD_SHADOW_LOAD);





	/*
	 *
	 * Action Qualifier Configuration in case of LLC_SYNCRECT_BY_PWM_TIMED
	 * If Position == H1L2
	 * - TBCTR = CMPA @UP -> PWMx HIGH
	 * - TBCTR = TBPRD -> PWMx LOW
	 *
	 * If Position == H2L1
	 * - TBCTR = CMPB @DOWN -> PWMx HIGH
	 * - TBCTR = ZERO -> PWMx LOW
	 */

    HWREGH(BaseAddress + EPWM_O_AQCTLA) = 0x0000;

	/*
	 * Generates PWM_A either from CMPA or CMPB (depends on Position)
	 */

	/**< Loads CMPA / CMPB on ZERO **/
	HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
	HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

	if (Position == FB_H1L2_BRIDGE) {

 		/**< Writes the init value into CMPA --> writes PRD in order to keep the output A LOW **/
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));

		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	}

	else if (Position == FB_H2L1_BRIDGE) {

 		/**< Writes the init value into CMPB --> writes ZERO in order to keep the output B LOW **/
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));

		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
	}

	else {
		/** does nothing **/
	}






	/*
	 * This setup is necessary in case of activation of HR (High Resolution) registers
	 * --> see 18.7.2 Dead-band Submodule Additional Operating Modes
	 * Otherwise the DB clock can be set as EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
	 */

    /**< Deadband bypassed on RED **/
	HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_RED, LLC_DB_RED_DELAY_MODE_DISABLE);
    /**< Deadband bypassed on FED --> this is not actually necessary since OUTB is generated by ePWM_A (RED)**/
	HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_FED, LLC_DB_RED_DELAY_MODE_DISABLE);

	/**< OUTA from ePWM_A **/
	HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_A, false);

	/**< OUTB from ePWM_A **/
	HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_B, true);










	/*
	 * High Resolution registers activation
	 */
	/*
	 * this configuration is recommended if the HighResolution feature shall be used
	 * see par. 18.15.1.5.4.1 High-Resolution Period Configuration
	 */
	/**< MEP control of rising edge (CMPAHR) **/
    HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_EDGE);
	/**< MEP control of rising edge (CMPBHR) **/
    HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_EDGE);


	/** NOTE FROM TRM
	* If the HRPWM module is configured in UP-DOWN counter mode, the shadow mode for the HRPWM
	* registers must be set to load on both ZERO AND PERIOD. New values from the user are loaded to
	* the shadow registers only at CTR=ZERO, but the shadow mode of for the registers must be set to
	* both ZERO AND PERIOD.
	**/
	/**< HRCMPA loaded on ZERO **/
	HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);
	/**< HRCMPB loaded on ZERO **/
	HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);

    HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL);
	HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL);

    HRPWM_enableAutoConversion(BaseAddress);

    HRPWM_enablePeriodControl(BaseAddress);

}

In attachment you also find 2 pictures: yellow line is ePWM1_A, green line is ePWM3_A
1701888899381.jpg: taken with CLKDIV = 0 and HSPCLKDIV = 1 for both ePWM
1701888899371.jpg: taken with CLKDIV = 0 and HSPCLKDIV = 1 for both ePWM1, CLKDIV = 0 and HSPCLKDIV = 0 for ePWM3

0 Prarthan Bhatt over 1 year ago in reply to Davide Dentoni

TI__Genius 9635 points

Can you send me all the epwm only configurations in file, the function you shared above only has hrpwm configurations can you share the pwm initializations also ?

Also have you tried examples for f28p65x that come in c2000ware maybe try those and change the values as mentioned in the code there is something off in the configurations.

0 Davide Dentoni over 1 year ago in reply to Prarthan Bhatt

Prodigy 175 points

For simplicity and finding the root cause to the issue can you remove/comment out all code pertaining to HRPWM and syncronizations just configure action qualifiers and see if the epwm outputs work as expected ?
Ok, I will do it but since my project is already at advanced development stage, this will take quite long time.

Can you send me all the epwm only configurations in file, the function you shared above only has hrpwm configurations can you share the pwm initializations also ?
I'm not sure I fully understood your question, anyway I try to answer:
in my project I'm using 6 ePWM to drive a PFC stage and 8 HRPWM to drive a CLLC full bridge stage.
In attached file "PFC_Config.c" you can find the configuration of ePWM used for PFC function.
each PWM peripherals used for CLLC functions is configured only by the function ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet that I already shared: there is not any other configuration as ePWM, just as HRPWM.
I add in attachment the file "LLC_Config.c" where I have added the function ABS_LLC_Enable_ePWM_Peripherals() - called before any other -
and the initialization function ABS_LLC_ConfigPWMs_LLCBridges(), that calls the configuration function ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet() and configures sync, phaseshift and reload links.

PFC_Config.c

static void ABS_PFC_ConfigSinglePfcPwm_DBDriven(const uint32_t base, const uint32_t period, const uint32_t CMPA, const uint32_t red, const uint32_t fed)
{
    //
    // =============================================== //
    // === Configure Time Base Submodule Registers === //
    // =============================================== //
    //
    // Enable TBPRD shadow load (Default is load on CTR=0)
    // PWM frequency = 1 / period
    // No phase shift
    // Initialize counter to 0
    // Configure counter for up-down count mode
    // Set prescalers: clock divider = 1, HS clock divider = 1
    // ---TBCLK = EPWMCLK/(HSPCLKDIV * CLKDIV)
    //
    EPWM_setPeriodLoadMode(base, EPWM_PERIOD_SHADOW_LOAD);
    EPWM_setTimeBasePeriod(base, (uint16_t)period);
    EPWM_setPhaseShift(base, 0);
	EPWM_setTimeBaseCounter(base, 0);
    EPWM_setEmulationMode(base, EPWM_EMULATION_FREE_RUN);
    EPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_setClockPrescaler(base, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //
    // =============================================== //
    // ===   Counter Compare Submodule Registers   === //
    // =============================================== //
    //
    // Set initial CMPA value, set duty 0% initially
    // Set initial CMPB value, set duty 0% initially
    // Enable CMPA shadow load on CTR = 0
    // Enable CMPB shadow load on CTR = 0
    //
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, (uint16_t)CMPA);
	EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);





    /*
	 * Clear AQCTLA, B and Deadband settings settings
     */
    HWREGH(base + EPWM_O_AQCTLA) = 0x0000;
    HWREGH(base + EPWM_O_AQCTLB) = 0x0000;
	HWREGH(base + EPWM_O_DBCTL) = 0x0000;






    //
    // =============================================== //
    // ===   Action Qualifier Submodule Registers  === //
    // =============================================== //
    //

    // CTR = CMPA@UP, EPWM_AQ_OUTPUT_A set to 0; CTR = CMPA@down, EPWM_AQ_OUTPUT_A set to 1
	/*	EPWM_AQ_OUTPUT_A is the only input to DB module and generates 2 complementary PWMs	*/
	EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A ,EPWM_AQ_OUTPUT_LOW,  EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A ,EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);






    //
    // =============================================== //
    // ===      Dead-Band Submodule Registers      === //
    // =============================================== //
    //
    // sets up the Dead Band counter clock rate with respect to TBCLK,Dead band counter runs at TBCLK rate
    EPWM_setDeadBandCounterClock(base,EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);

    // enables and sets the Dead Band control register shadow load mode
	EPWM_setDeadBandControlShadowLoadMode(base, EPWM_DB_LOAD_ON_CNTR_ZERO);

    // sets the Rising Edge Delay register shadow load mode
    EPWM_setRisingEdgeDelayCountShadowLoadMode(base, EPWM_RED_LOAD_ON_CNTR_ZERO);

    // enables and sets the Falling Edge Delay register shadow load mode
	EPWM_setFallingEdgeDelayCountShadowLoadMode(base, EPWM_FED_LOAD_ON_CNTR_ZERO);

    // Rising Edge delay input signal is EPWMA
    EPWM_setRisingEdgeDeadBandDelayInput(base, EPWM_DB_INPUT_EPWMA);

    // Falling Edge delay input signal is EPWMA
    EPWM_setFallingEdgeDeadBandDelayInput(base, EPWM_DB_INPUT_EPWMA);




    // RED (Rising Edge Delay) count
    EPWM_setRisingEdgeDelayCount(base, (uint16_t)red);
    // FED (Falling Edge Delay) count
    EPWM_setFallingEdgeDelayCount(base, (uint16_t)fed);

    // polarity of rising Edge delay is not inverted
    EPWM_setDeadBandDelayPolarity(base, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    // polarity of falling Edge delay is inverted.
    EPWM_setDeadBandDelayPolarity(base, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
    // Rising edge delay is applied
    EPWM_setDeadBandDelayMode(base, EPWM_DB_RED, PFC_DB_RED_DELAY_MODE_ENABLE);
	// Falling edge edge delay is applied
    EPWM_setDeadBandDelayMode(base ,EPWM_DB_FED, PFC_DB_FED_DELAY_MODE_ENABLE);

}

LLC_Config.c

static void ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet(uint32_t BaseAddress, uint16_t PeriodCountReload, LLCBRIDGE_Position_t Position)
{

    uint32_t pwmPeriod_ticks;


	/*
	 * compute PERIOD reload value to be loaded in HR registers
	 */
	pwmPeriod_ticks = (uint32_t)((float32_t)PeriodCountReload * 65536.0f);/* polyspace MISRA2012:10.8 [Justified:Low] "cast needed by application" */



    /*
	 * Direct access to HR PERIOD register
	 * should be faster than using drivers
	 */
    HRPWM_setTimeBasePeriod(BaseAddress, pwmPeriod_ticks);


    HRPWM_setTimeBaseCounter(BaseAddress, 0);
    HRPWM_setPhaseShift(BaseAddress, 0);
    HRPWM_setTimeBaseCounterMode(BaseAddress, EPWM_COUNTER_MODE_UP_DOWN);
    HRPWM_setEmulationMode(BaseAddress, EPWM_EMULATION_FREE_RUN);
	
	/**< Set the dividers in order to match the value of EPWMCLK_LLC **/
	HRPWM_setClockPrescaler(BaseAddress, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2);



	/**< Loads TBPRD on PERIOD **/
    HRPWM_setPeriodLoadMode(BaseAddress, EPWM_PERIOD_SHADOW_LOAD);





	/*
	 *
	 * Action Qualifier Configuration in case of LLC_SYNCRECT_BY_PWM_TIMED
	 * If Position == H1L2
	 * - TBCTR = CMPA @UP -> PWMx HIGH
	 * - TBCTR = TBPRD -> PWMx LOW
	 *
	 * If Position == H2L1
	 * - TBCTR = CMPB @DOWN -> PWMx HIGH
	 * - TBCTR = ZERO -> PWMx LOW
	 */

    HWREGH(BaseAddress + EPWM_O_AQCTLA) = 0x0000;

	/*
	 * Generates PWM_A either from CMPA or CMPB (depends on Position)
	 */

	/**< Loads CMPA / CMPB on ZERO **/
	HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
	HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

	if (Position == FB_H1L2_BRIDGE) {

 		/**< Writes the init value into CMPA --> writes PRD in order to keep the output A LOW **/
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));

		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	}

	else if (Position == FB_H2L1_BRIDGE) {

 		/**< Writes the init value into CMPB --> writes ZERO in order to keep the output B LOW **/
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));

		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
	}

	else {
		/** does nothing **/
	}






	/*
	 * This setup is necessary in case of activation of HR (High Resolution) registers
	 * --> see 18.7.2 Dead-band Submodule Additional Operating Modes
	 * Otherwise the DB clock can be set as EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
	 */

    /**< Deadband bypassed on RED **/
	HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_RED, LLC_DB_RED_DELAY_MODE_DISABLE);
    /**< Deadband bypassed on FED --> this is not actually necessary since OUTB is generated by ePWM_A (RED)**/
	HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_FED, LLC_DB_RED_DELAY_MODE_DISABLE);

	/**< OUTA from ePWM_A **/
	HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_A, false);

	/**< OUTB from ePWM_A **/
	HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_B, true);










	/*
	 * High Resolution registers activation
	 */
	/*
	 * this configuration is recommended if the HighResolution feature shall be used
	 * see par. 18.15.1.5.4.1 High-Resolution Period Configuration
	 */
	/**< MEP control of rising edge (CMPAHR) **/
    HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_EDGE);
	/**< MEP control of rising edge (CMPBHR) **/
    HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_EDGE);


	/** NOTE FROM TRM
	* If the HRPWM module is configured in UP-DOWN counter mode, the shadow mode for the HRPWM
	* registers must be set to load on both ZERO AND PERIOD. New values from the user are loaded to
	* the shadow registers only at CTR=ZERO, but the shadow mode of for the registers must be set to
	* both ZERO AND PERIOD.
	**/
	/**< HRCMPA loaded on ZERO **/
	HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);
	/**< HRCMPB loaded on ZERO **/
	HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);

    HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL);
	HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL);

    HRPWM_enableAutoConversion(BaseAddress);

    HRPWM_enablePeriodControl(BaseAddress);

}








/**< This function provides the clock to PWM used **/
void ABS_LLC_Enable_ePWM_Peripherals(void)
{


	/** Safety Manual par 4.2.6 - comma 1 - CLK14-Peripheral clock gating **/
    /* Peripherals for Primary LLC */
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM18);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12);

	/**< Burst mode gating primary **/
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM17);




	/* Peripherals for Secondary LLC */
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM13);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9);

	/**< Burst mode gating Secondary **/
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10);








	/* This is necessary to use the High Resolution modulator --> see par. 18.15.1.2 HRPWM Source Clock */
	/** Safety Manual par 4.2.6 - comma 1 - CLK14-Peripheral clock gating **/
	SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL0);
	SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL1);
	SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL2);

}







/**--------------------------------------------------------------------------
 * @fn			void ABS_LLC_ConfigPWMs_LLCBridges(void)
 * @brief		configures LLC ePWMs peripherals in order to generate synchronous rectification switching ON the synchronous PWM
 *				in sync with driving PWM, and switching OFF based on CMPSSx output
 * @details		Configures Phase Shift, SYNC Input source, TBPRD register link, CMPA/CMPB register link
 * @param[in]
 * @calls
 * @return
 */
static void ABS_LLC_ConfigPWMs_LLCBridges(void)
{

	uint8_least Counter;

	Counter = 0;
	
	/*
	 *< REMARK FOR TI SUPPORT
	 * THIS LOOP CONFIGURES THE PWMs OF CLLC BRIDGE, DEPENDING ON THEIR POSITION IN THE BRIDGE
	 * USES FUNCTION ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet THAT IS WRITTEN ABOVE
	 */
	while (Counter < NOF_LLC_PWMs) {
		ABS_LLC_PWMsTab_Descriptor_t *LLCTabDescriptorPtr;

		LLCTabDescriptorPtr = &TAB_ePWM_LLC_TableDescriptor[Counter];

		/*
		 * Configures the single pwm depending on the PWM position in LLC bridge
		 * All PWMS are configured as UP DOWN counter
		 */
		ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet(LLCTabDescriptorPtr->PWM_BaseAddress, (uint16_t)LLC_MIN_PRD_UD_MODE_COUNT, LLCTabDescriptorPtr->PWM_Position);

		Counter = Counter + 1u;
	}




	/*
	 * Sets the shift phase and register links between ePWMs
	 */
	/**< PWM PRI LEG1 HS --> generates SYNCOUT **/
	EPWM_disablePhaseShiftLoad(LLC_PRI_LEG1_HS_PWM_MODULE);
	EPWM_enableSyncOutPulseSource(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);



	/*
	 * PWM PRI LEG1 LS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 */
    EPWM_enablePhaseShiftLoad(LLC_PRI_LEG1_LS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);



	/*
	 * PWM PRI LEG2 HS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPB register is linked to PRI LEG1 LS
	 */
    EPWM_enablePhaseShiftLoad(LLC_PRI_LEG2_HS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);
	/** CMPB linked to CMPB of PRI 1 LS (ePWM18) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_B);

	/** CMPA linked to CMPA of PRI 1 LS (ePWM18) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A);



	/*
	 * PWM PRI LEG2 LS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPA register is linked to PRI LEG1 HS
	 */
    EPWM_enablePhaseShiftLoad(LLC_PRI_LEG2_LS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);
	/** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A);

	/** CMPB linked to CMPB of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_B);


	/**< Enables the ONE SHOT SYNC output --> used by PRI GATING BURST PWM to sync when entering BURST MODE **/
	/**< This needs also the standard sync out enabled, because the synch-ed output takes as source the std sync out  **/
	/**< PAY ATTENTION: this is only a enable: SYNC must be commanded by sw **/
	EPWM_enableSyncOutPulseSource(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);
	EPWM_enableOneShotSync(LLC_PRI_LEG2_LS_PWM_MODULE);







	/*
	 * PWM SEC LEG1 HS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPA register is linked to PRI LEG1 HS
	 */
    EPWM_enablePhaseShiftLoad(LLC_SEC_LEG1_HS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);
	/** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A);



	/*
	 * PWM SEC LEG1 LS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPB register is linked to PRI LEG1 LS
	 */
    EPWM_enablePhaseShiftLoad(LLC_SEC_LEG1_LS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);

	/** CMPA linked to CMPA of PRI 1 LS (ePWM18) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A);



	/*
	 * PWM SEC LEG2 HS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPB register is linked to PRI LEG1 LS
	 */
    EPWM_enablePhaseShiftLoad(LLC_SEC_LEG2_HS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);

	/** CMPA linked to CMPA of SEC 1 LS (ePWM7) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A);

	/** CMPB linked to CMPB of PRI 1 LS (ePWM18) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_COMP_B);




	/*
	 * PWM SEC LEG2 LS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPA register is linked to PRI LEG1 HS
	 */
    EPWM_enablePhaseShiftLoad(LLC_SEC_LEG2_LS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);
	/** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A);


	/** CMP3 linked to CMP3 of SEC 1 HS (ePWM13) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_13, EPWM_LINK_COMP_B);



	/**< Enables the ONE SHOT SYNC output --> used by SEC GATING BURST PWM to sync when entering BURST MODE **/
	/**< This needs also the standard sync out enabled, because the synch-ed output takes as source the std sync out  **/
	/**< PAY ATTENTION: this is only a enable: SYNC must be commanded by sw **/
	EPWM_enableSyncOutPulseSource(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);
	EPWM_enableOneShotSync(LLC_SEC_LEG2_LS_PWM_MODULE);









	/*
	 * Sets the initial compare value of CMPC --> used to trigger AD conversion of HVDC I / HVDC V
	 * CMPC is set in the middle of duty cycle of PWMxA HIGH
	 * This feature is used only with Primary LLC pwm to generate a SOC for IBAT and VBAT
	 */
	EPWM_setCounterCompareValue(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_COUNTER_COMPARE_C, (LLC_MIN_PRD_UD_MODE_COUNT >> 1u));


	/*
	 * Sets the LoadMode of CMPC --> used to trigger AD conversion
	 */
	EPWM_setCounterCompareShadowLoadMode(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_COUNTER_COMPARE_C, EPWM_COMP_LOAD_ON_CNTR_ZERO);


}

Also have you tried examples for f28p65x that come in c2000ware maybe try those and change the values as mentioned in the code there is something off in the configurations
Honestly I still did not. I will check if I can find some example fitting my needs.

I add some more details about my project for your better understanding:
HRPWMs peripherals are: PWM1,PWM2,PWM3,PWM7,PWM9,PWM12,PWM13,PWM18, all configured using the function ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet()
PWM1,PWM9,PWM12 and PWM13 are configured with Position = FB_H1L2_BRIDGE, therefore the action qualifier is "HIGH on CMPA when counting UP, LOW on CMPB when counting UP"
They all work properly.

PWM2,PWM3,PWM7 and PWM18 are configured with Position = FB_H2L1_BRIDGE, therefore the action qualifier is "HIGH on CMPA when counting DOWN, LOW on CMPB when counting DOWN"
They ALL don't work: no PWM signal.
That's why I was focusing on some issue linked to the down counting.
And remind what I have previously written: if I change the AQCTLA configuration of PWM2,PWM3,PWM7 and PWM18 to "HIGH on CMPA when counting UP, LOW on CMPB when counting UP", the PWM is generated.

Some questions from my side:
had you the chance to test my configuration? I think using only PWM2 and PWM3 is enough to feel the different behavior.
Same behavior was seen on both EVA board (Docking + ControlCard) and the final board.

0 Prarthan Bhatt over 1 year ago in reply to Davide Dentoni

TI__Genius 9635 points

Thank you for the details.

As I am going through the code you set compare values using variable LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint) so just to make sure you have verified that CMPA and CMPB values match your expectations as below.
Because if CMPA is not greater than CMPB there wont be any pulse output can you also send me a snapshot or register view dump when there is no pwm output for these pwms.

Davide Dentoni said:
"HIGH on CMPA when counting DOWN, LOW on CMPB when counting DOWN

Davide Dentoni said:
ePWM3.CMPA = 0x009C0000
ePWM3.CMPB = 0x000A0000

I have tried with basic epwm configuration like just setting action qualifiers and cmpa, cmpb values on up-down count mode and I see pwm output both on A and B.

Thanks

0 Davide Dentoni over 1 year ago in reply to Prarthan Bhatt

Prodigy 175 points

Hello
"As I am going through the code you set compare values using variable LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint) so just to make sure you have verified that CMPA and CMPB values match your expectations as below.
Because if CMPA is not greater than CMPB there wont be any pulse output can you also send me a snapshot or register view dump when there is no pwm output for these pwms."

I did not explain that function ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet just make the initial configuration with the aim to configure everithing but keeping outputs OFF.

In runtime CMPA and CMPB take different values (variable frequency).
Pair
ePWM3.CMPA = 0x009C0000
ePWM3.CMPB = 0x000A0000
is one configuration that is supposed to work and it does not.

"I have tried with basic epwm configuration like just setting action qualifiers and cmpa, cmpb values on up-down count mode and I see pwm output both on A and B."
Could you please try with HRPWM ? Maybe you can do this test faster than me.
Please, remind to set
SYSCLK = 200MHz, and
EPWMCLK = 200MHz (PERCLKDIVSEL.EPWMCLKDIV = 0)

Best regards

0 Davide Dentoni over 1 year ago in reply to Davide Dentoni

Prodigy 175 points

Hello
I have tested my project using ePWM instead of HRPWM and the issue is not present.

In details:
I have deleted from function ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet() all the final part after the
comment "High Resolution registers activation",
and I have replaced
HRPWM_setTimeBasePeriod
HRPWM_setPhaseShift
HRPWM_setCounterCompareValue
with corresponding epwm functions.

Many other hrpwm functions are merely a redefinition of epmw and didn't need to be replaced.
Of course, also the follwing have been deleted
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL0);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL2);

Now the question remains:
what is the link between the following 3 features:
- PWM output qualified in down count
- PWM set in High Resolution
- PWM TBCLK (100MHz) different than EPWMCLK (200MHz)

If I change one of the three settings above, the PWM works.

0 Prarthan Bhatt over 1 year ago in reply to Davide Dentoni

TI__Genius 9635 points

Hello Davide,

Lets dig into your High resolution settings since I do not expect anything wrong with TBCLK being 200Mhz or 100Mhz both should work :

Are you initializing the SFO() function for the MEP scale factor to be acquired using the SFO() function ?
Also refer to steps highlighted in section 22.18.1.5.4.1 High-Resolution Period Configuration to see if you are missing any ?

Also because you are using HRPE high resolution period making sure you are aware of the below limitation pertaining to min and max duty cycles ?
Please refer to section 22.18.1.5.3 Duty Cycle Range Limitation

Thanks

0 Davide Dentoni over 1 year ago in reply to Prarthan Bhatt

Prodigy 175 points

Hello,
you wrote: "Are you initializing the SFO() function for the MEP scale factor to be acquired using the SFO() function ?" Yes

you wrote: "Also refer to steps highlighted in section 22.18.1.5.4.1 High-Resolution Period Configuration to see if you are missing any ?"
Referring to the par. "22.18.1.5.4.1 High-Resolution Period Configuration", this is the initialization sequence in my project:
- EPWMClockDivider clock divider setting (field SYSCTL_O_PERCLKDIVSEL)
- Enable ePWMx clock
- Enable HRPWMx clock
- Disable TBCLKSYNC
- Launch of function SFO() to initiate the MEP module
- Configuration of ePWMx registers: this is done by the function ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet() already shared
and includes:
    - CMPCTL[LOADAMODE] = EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD (2), through function HRPWM_setCounterCompareShadowLoadMode()
   - HRCNFG[HRLOAD] = HRPWM_LOAD_ON_CNTR_ZERO_PERIOD (2), through function HRPWM_setCounterCompareShadowLoadEvent()
   - HRCNFG[AUTOCONV] = 1, through function HRPWM_enableAutoConversion()
   - HRCNFG[EDGMODE] = HRPWM_MEP_CTRL_RISING_EDGE (1), through function HRPWM_setMEPEdgeSelect() --> setting value is different than the one suggested by TRM (3), and the function is called not respecting the same order as in TRM (is the order so important ?)
   - Enable high-resolution period control (HRPCTL[HRPE] = 1), through function HRPWM_enablePeriodControl --> function is called not respecting the same order as in TRM
    - Setting of and TBCTL[PHSEN] = 1 through EPWM_enablePhaseShiftLoad --> function is called not respecting the same order as in TRM
- Enable TBCLKSYNC
- TBCTL[SWFSYNC] = 1
- Periodic acquiring of MEP scale factor using SFO function()

I have also made a test modifying the sequence above as follows:
- HRCNFG[EDGMODE], called with the proper argument (3) and respecting the same order as TRM
- Enabling high-resolution period control (HRPCTL[HRPE] = 1), called respecting the same order as TRM
- Setting of and TBCTL[PHSEN] = 1 through EPWM_enablePhaseShiftLoad, called respecting the same order as TRM
- Adding setup of HRPCTL[TBPSHRLOADE] = 1, this setting was missing

Result is the same as before: this does not surprise me because, as I wrote previously, I can see PWM in output if I change on the fly into debugger the value of HSPCLKDIV from 1 to 0.
This suggests to me that the PWm configuration, even is not exactly the same as in TRM, is not the root cause of this issue.

You wrote
"Also because you are using HRPE high resolution period making sure you are aware of the below limitation pertaining to min and max duty cycles cycles ? Please refer to section 22.18.1.5.3 Duty Cycle Range Limitation"

I previously wrote you the values of CMPA/CMPB and PRD during the issue:
ePWM1.CMPA = 0x000A0000
ePWM1.CMPB = 0x009C0000

ePWM3.CMPA = 0x009C0000
ePWM3.CMPB = 0x000A0000

ePWM1.TBPRD = ePWM3.TBPRD = 0x00A6
ePWM1.TBPRDHR = ePWM3.TBPRDHR = 0x0000
I think those values are not violating the limitations of section 22.18.1.5.3.

Have you tried my configuration ?

0 Prarthan Bhatt over 1 year ago in reply to Davide Dentoni

TI__Genius 9635 points

Based on the CMPA and CMPB values of A000 and 9C0000 the upper 8 bits of CMPAHR and CMPBHR would be zero as shown below

But according to definition If the AUTOCONV bit (HRCNFG.6) is set and the MEP_ScaleFactor is in the HRMSTEP register, then CMPAHR / CMPBHR register value = frac (PWMDuty*PWMperiod<<8)

Can you set the CMPAHR and CMPBHR accordingly ? You can refer to the ex4 for hrpwm where the duty cycle is steeped up from minduty cycle and CMPAHR is calculated in loop as shown in snapshot below

I will try to prepare the code files as per your configuration it would be faster if you could just send me cut down version of your code settings just for one pwm which leads to the issue which I can just copy paste in empty project and run.

Thanks

0 Prarthan Bhatt over 1 year ago in reply to Prarthan Bhatt

TI__Genius 9635 points

Also I checked with the internal team on the clocking for HRPWM, there is a requirement for the TBCLK to be the same as HRPWM CLK. That's why its imperative to have HSPCLKDIV and CLKDIV to be 1 so that TBCLK and HRPWM CLK equal.

0 Davide Dentoni over 1 year ago in reply to Prarthan Bhatt

Prodigy 175 points

Hello,
thank you for your last suggestions.

You wrote
"I will try to prepare the code files as per your configuration it would be faster if you could just send me cut down version of your code settings just for one pwm which leads to the issue which I can just copy paste in empty project and run."
The function ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet() that I already shared is the most representative of my setting for 1 pwm.
I attach here a version with all the necessary definition and data types.
You should first set
SYSCLK = 200MHz
EPWMCLK = 200MHz (PERCLKDIVSEL.EPWMCLKDIV = 0)

then call the function ABS_LLC_Enable_ePWM_Peripherals() to provide the clock to PWMs
and as last call ABS_LLC_ConfigPWMs_LLCBridges(), that configures all PWMs, but for you test you can focus on just PWM1 and PWM3 (easiest to catch on EVA board)

LLC_Config_1.c

#define LLC_BUS_FREQUENCY							(100e6)
#define LLC_MAX_FREQUENCY                   		((float32_t)350000.0)
#define LLC_PERIOD_RELOAD_RATIO						(2u)

#define LLC_MIN_PRD_UD_MODE_COUNT					(uint32_t)((LLC_BUS_FREQUENCY / (float32_t)(LLC_MAX_FREQUENCY * LLC_PERIOD_RELOAD_RATIO)))

#define LLC_PWM_HR_TRANSFORM(Count)					(uint32_t)((uint32_t)Count << 16u)

#define NOF_PWMs_PRIMARY_STAGE						(4u)
#define NOF_PWMs_SECONDARY_STAGE					(4u)
#define NOF_LLC_PWMs								(NOF_PWMs_PRIMARY_STAGE + NOF_PWMs_SECONDARY_STAGE)


#define LLC_PRI_LEG1_HS_PWM_MODULE					(EPWM1_BASE)
#define LLC_PRI_LEG1_LS_PWM_MODULE					(EPWM18_BASE)
#define LLC_PRI_LEG2_HS_PWM_MODULE					(EPWM3_BASE)
#define LLC_PRI_LEG2_LS_PWM_MODULE					(EPWM12_BASE)

#define LLC_SEC_LEG1_HS_PWM_MODULE					(EPWM13_BASE)
#define LLC_SEC_LEG1_LS_PWM_MODULE					(EPWM2_BASE)
#define LLC_SEC_LEG2_HS_PWM_MODULE					(EPWM7_BASE)
#define LLC_SEC_LEG2_LS_PWM_MODULE					(EPWM9_BASE)


typedef enum LLC_PWM_Out_e {
	PWM_OutA = 1,
	PWM_OutB = 2,
} LLC_PWM_Out_t;



typedef enum LLCBRIDGE_Position_e {
	FB_H1L2_BRIDGE = 1u,
	FB_H2L1_BRIDGE = 2u,
} LLCBRIDGE_Position_t;



typedef struct /*ABS_LLC_PWMsTab_Descriptor_s */{
	uint32_t				PWM_BaseAddress;
	LLC_PWM_Out_t			PWM_Out;
	LLCBRIDGE_Position_t	PWM_Position;
} ABS_LLC_PWMsTab_Descriptor_t;



static ABS_LLC_PWMsTab_Descriptor_t TAB_ePWM_LLC_TableDescriptor[NOF_LLC_PWMs] = {
	{	LLC_PRI_LEG1_HS_PWM_MODULE, PWM_OutA, FB_H1L2_BRIDGE },
	{	LLC_PRI_LEG1_LS_PWM_MODULE,	PWM_OutB, FB_H2L1_BRIDGE },
	{	LLC_PRI_LEG2_HS_PWM_MODULE, PWM_OutA, FB_H2L1_BRIDGE },
	{	LLC_PRI_LEG2_LS_PWM_MODULE, PWM_OutA, FB_H1L2_BRIDGE },

	{	LLC_SEC_LEG1_HS_PWM_MODULE,	PWM_OutB, FB_H1L2_BRIDGE },
	{	LLC_SEC_LEG1_LS_PWM_MODULE, PWM_OutA, FB_H2L1_BRIDGE },
	{	LLC_SEC_LEG2_HS_PWM_MODULE, PWM_OutA, FB_H2L1_BRIDGE },
	{	LLC_SEC_LEG2_LS_PWM_MODULE, PWM_OutA, FB_H1L2_BRIDGE },




static void ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet(uint32_t BaseAddress, uint16_t PeriodCountReload, LLCBRIDGE_Position_t Position)
{

    uint32_t pwmPeriod_ticks;


	/*
	 * compute PERIOD reload value to be loaded in HR registers
	 */
	pwmPeriod_ticks = (uint32_t)((float32_t)PeriodCountReload * 65536.0f);/* polyspace MISRA2012:10.8 [Justified:Low] "cast needed by application" */



    /*
	 * Direct access to HR PERIOD register
	 * should be faster than using drivers
	 */
    HRPWM_setTimeBasePeriod(BaseAddress, pwmPeriod_ticks);


    HRPWM_setTimeBaseCounter(BaseAddress, 0);
    HRPWM_setPhaseShift(BaseAddress, 0);
    HRPWM_setTimeBaseCounterMode(BaseAddress, EPWM_COUNTER_MODE_UP_DOWN);
    HRPWM_setEmulationMode(BaseAddress, EPWM_EMULATION_FREE_RUN);
	
	/**< Set the dividers in order to match the value of EPWMCLK_LLC **/
	HRPWM_setClockPrescaler(BaseAddress, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2);



	/**< Loads TBPRD on PERIOD **/
    HRPWM_setPeriodLoadMode(BaseAddress, EPWM_PERIOD_SHADOW_LOAD);





	/*
	 *
	 * Action Qualifier Configuration in case of LLC_SYNCRECT_BY_PWM_TIMED
	 * If Position == H1L2
	 * - TBCTR = CMPA @UP -> PWMx HIGH
	 * - TBCTR = TBPRD -> PWMx LOW
	 *
	 * If Position == H2L1
	 * - TBCTR = CMPB @DOWN -> PWMx HIGH
	 * - TBCTR = ZERO -> PWMx LOW
	 */

    HWREGH(BaseAddress + EPWM_O_AQCTLA) = 0x0000;

	/*
	 * Generates PWM_A either from CMPA or CMPB (depends on Position)
	 */

	/**< Loads CMPA / CMPB on ZERO **/
	HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
	HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

	if (Position == FB_H1L2_BRIDGE) {

 		/**< Writes the init value into CMPA --> writes PRD in order to keep the output A LOW **/
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(0x000A));
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(0x009C));

		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	}

	else if (Position == FB_H2L1_BRIDGE) {

 		/**< Writes the init value into CMPB --> writes ZERO in order to keep the output B LOW **/
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(0x009C));
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(0x000A));

		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
	}

	else {
		/** does nothing **/
	}






	/*
	 * This setup is necessary in case of activation of HR (High Resolution) registers
	 * --> see 18.7.2 Dead-band Submodule Additional Operating Modes
	 * Otherwise the DB clock can be set as EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
	 */

    /**< Deadband bypassed on RED **/
	HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_RED, LLC_DB_RED_DELAY_MODE_DISABLE);
    /**< Deadband bypassed on FED --> this is not actually necessary since OUTB is generated by ePWM_A (RED)**/
	HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_FED, LLC_DB_RED_DELAY_MODE_DISABLE);

	/**< OUTA from ePWM_A **/
	HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_A, false);

	/**< OUTB from ePWM_A **/
	HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_B, true);










	/*
	 * High Resolution registers activation
	 */
	/*
	 * this configuration is recommended if the HighResolution feature shall be used
	 * see par. 18.15.1.5.4.1 High-Resolution Period Configuration
	 */
	/**< MEP control of rising edge (CMPAHR) **/
    HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_EDGE);
	/**< MEP control of rising edge (CMPBHR) **/
    HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_EDGE);


	/** NOTE FROM TRM
	* If the HRPWM module is configured in UP-DOWN counter mode, the shadow mode for the HRPWM
	* registers must be set to load on both ZERO AND PERIOD. New values from the user are loaded to
	* the shadow registers only at CTR=ZERO, but the shadow mode of for the registers must be set to
	* both ZERO AND PERIOD.
	**/
	/**< HRCMPA loaded on ZERO **/
	HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);
	/**< HRCMPB loaded on ZERO **/
	HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);

    HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL);
	HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL);

    HRPWM_enableAutoConversion(BaseAddress);

    HRPWM_enablePeriodControl(BaseAddress);

}








/**--------------------------------------------------------------------------
 * @fn			void ABS_LLC_ConfigPWMs_LLCBridges(void)
 * @brief		configures LLC ePWMs peripherals in order to generate synchronous rectification switching ON the synchronous PWM
 *				in sync with driving PWM, and switching OFF based on CMPSSx output
 * @details		Configures Phase Shift, SYNC Input source, TBPRD register link, CMPA/CMPB register link
 * @param[in]
 * @calls
 * @return
 */
static void ABS_LLC_ConfigPWMs_LLCBridges(void)
{

	uint8_least Counter;

	Counter = 0;
	
	/*
	 *< REMARK FOR TI SUPPORT
	 * THIS LOOP CONFIGURES THE PWMs OF CLLC BRIDGE, DEPENDING ON THEIR POSITION IN THE BRIDGE
	 * USES FUNCTION ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet THAT IS WRITTEN ABOVE
	 */
	while (Counter < NOF_LLC_PWMs) {
		ABS_LLC_PWMsTab_Descriptor_t *LLCTabDescriptorPtr;

		LLCTabDescriptorPtr = &TAB_ePWM_LLC_TableDescriptor[Counter];

		/*
		 * Configures the single pwm depending on the PWM position in LLC bridge
		 * All PWMS are configured as UP DOWN counter
		 */
		ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet(LLCTabDescriptorPtr->PWM_BaseAddress, (uint16_t)LLC_MIN_PRD_UD_MODE_COUNT, LLCTabDescriptorPtr->PWM_Position);

		Counter = Counter + 1u;
	}




	/*
	 * Sets the shift phase and register links between ePWMs
	 */
	/**< PWM PRI LEG1 HS --> generates SYNCOUT **/
	EPWM_disablePhaseShiftLoad(LLC_PRI_LEG1_HS_PWM_MODULE);
	EPWM_enableSyncOutPulseSource(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);



	/*
	 * PWM PRI LEG1 LS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 */
    EPWM_enablePhaseShiftLoad(LLC_PRI_LEG1_LS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);



	/*
	 * PWM PRI LEG2 HS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPB register is linked to PRI LEG1 LS
	 */
    EPWM_enablePhaseShiftLoad(LLC_PRI_LEG2_HS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);
	/** CMPB linked to CMPB of PRI 1 LS (ePWM18) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_B);

	/** CMPA linked to CMPA of PRI 1 LS (ePWM18) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A);



	/*
	 * PWM PRI LEG2 LS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPA register is linked to PRI LEG1 HS
	 */
    EPWM_enablePhaseShiftLoad(LLC_PRI_LEG2_LS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);
	/** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A);

	/** CMPB linked to CMPB of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_B);


	/**< Enables the ONE SHOT SYNC output --> used by PRI GATING BURST PWM to sync when entering BURST MODE **/
	/**< This needs also the standard sync out enabled, because the synch-ed output takes as source the std sync out  **/
	/**< PAY ATTENTION: this is only a enable: SYNC must be commanded by sw **/
	EPWM_enableSyncOutPulseSource(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);
	EPWM_enableOneShotSync(LLC_PRI_LEG2_LS_PWM_MODULE);







	/*
	 * PWM SEC LEG1 HS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPA register is linked to PRI LEG1 HS
	 */
    EPWM_enablePhaseShiftLoad(LLC_SEC_LEG1_HS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);
	/** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A);



	/*
	 * PWM SEC LEG1 LS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPB register is linked to PRI LEG1 LS
	 */
    EPWM_enablePhaseShiftLoad(LLC_SEC_LEG1_LS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);

	/** CMPA linked to CMPA of PRI 1 LS (ePWM18) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A);



	/*
	 * PWM SEC LEG2 HS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPB register is linked to PRI LEG1 LS
	 */
    EPWM_enablePhaseShiftLoad(LLC_SEC_LEG2_HS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);

	/** CMPA linked to CMPA of SEC 1 LS (ePWM7) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A);

	/** CMPB linked to CMPB of PRI 1 LS (ePWM18) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_COMP_B);




	/*
	 * PWM SEC LEG2 LS
	 * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter
	 * TBPRD is linked to PRI LEG1 HS
	 * CMPA register is linked to PRI LEG1 HS
	 */
    EPWM_enablePhaseShiftLoad(LLC_SEC_LEG2_LS_PWM_MODULE);
	/** Sets the Sync In from Sync Out of the master (PWM8) **/
	EPWM_setSyncInPulseSource(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    /** Count up after sync **/
	EPWM_setCountModeAfterSync(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
	/** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);
	/** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A);


	/** CMP3 linked to CMP3 of SEC 1 HS (ePWM13) **/
	EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_13, EPWM_LINK_COMP_B);



	/**< Enables the ONE SHOT SYNC output --> used by SEC GATING BURST PWM to sync when entering BURST MODE **/
	/**< This needs also the standard sync out enabled, because the synch-ed output takes as source the std sync out  **/
	/**< PAY ATTENTION: this is only a enable: SYNC must be commanded by sw **/
	EPWM_enableSyncOutPulseSource(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);
	EPWM_enableOneShotSync(LLC_SEC_LEG2_LS_PWM_MODULE);









	/*
	 * Sets the initial compare value of CMPC --> used to trigger AD conversion of HVDC I / HVDC V
	 * CMPC is set in the middle of duty cycle of PWMxA HIGH
	 * This feature is used only with Primary LLC pwm to generate a SOC for IBAT and VBAT
	 */
	EPWM_setCounterCompareValue(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_COUNTER_COMPARE_C, (LLC_MIN_PRD_UD_MODE_COUNT >> 1u));


	/*
	 * Sets the LoadMode of CMPC --> used to trigger AD conversion
	 */
	EPWM_setCounterCompareShadowLoadMode(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_COUNTER_COMPARE_C, EPWM_COMP_LOAD_ON_CNTR_ZERO);

}










/**< This function provides the clock to PWM used **/
void ABS_LLC_Enable_ePWM_Peripherals(void)
{


	/** Safety Manual par 4.2.6 - comma 1 - CLK14-Peripheral clock gating **/
    /* Peripherals for Primary LLC */
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM18);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12);

	/**< Burst mode gating primary **/
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM17);




	/* Peripherals for Secondary LLC */
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM13);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9);

	/**< Burst mode gating Secondary **/
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10);








	/* This is necessary to use the High Resolution modulator --> see par. 18.15.1.2 HRPWM Source Clock */
	/** Safety Manual par 4.2.6 - comma 1 - CLK14-Peripheral clock gating **/
	SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL0);
	SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL1);
	SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL2);

}

You wrote
"Also I checked with the internal team on the clocking for HRPWM, there is a requirement for the TBCLK to be the same as HRPWM CLK. That's why its imperative to have HSPCLKDIV and CLKDIV to be 1 so that TBCLK and HRPWM CLK equal."
Independent on my PWWs setting or the management of MEP, I think this sentence is quite definitive.
Could you also tell me at which par. of TRM this is written ? Have I missed it ?

+1 Prarthan Bhatt over 1 year ago in reply to Davide Dentoni

TI__Genius 9635 points

Davide Dentoni said:
Independent on my PWWs setting or the management of MEP, I think this sentence is quite definitive.
Could you also tell me at which par. of TRM this is written ? Have I missed it ?

Its not documented in TRM will be included in the next revision of TRM. I confirmed with internal team that it is applicable to F28P65x

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TMS320F28P659DK-Q1: ePWM unexpected behavior when TBCTR is counting down