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TMS320F28379D: Configure emif1 to access sdram device using less pins

Clecio Jung
Prodigy 20 points
Part Number: TMS320F28379D

Due to most of the processor pins being used, my company chose not to connect the EM1A11 and EM1A10 pins to the SDRAM, thinking that this would only sacrifice some addresses (the processor is using these pins for the SPI interface). But now, reading the documentation, I realize that the EM1A10 pin has a specific functionality related to the PRE command. Is it possible to communicate with SDRAM memory without using these pins? And what would the configuration of the EMIF registers be like in this case?

SDRAM being used: AS4C8M32S-6TIN 256Mbits x 16 bits x 4 banks

  • 0
    TI__Mastermind 30185 points

    Hello Clecio,

    Seeing that the PRE is used in the datasheet of the SDRAM you mentioned, it seems like it may be necessary but I will confirm with another expert to make sure and see what the impact might be based on not having that pin available.

    Clecio Jung said:
    And what would the configuration of the EMIF registers be like in this case?

    Can you be more specific regarding which registers you're talking about? Please list the EMIF or EMIF configuration registers you have questions on specifically.

  • 0 in reply to Omer Amir
    Prodigy 20 points

    Hello Omer. Thanks for the support.

    I'm more interested in the configuration of the register CR (SDRAM_CR). Normally, for this SDRAM, I wold configure it like this:

    // IBANK=2 (4 banks), PAGESIZE=1 (512 words 9 column address bits), CL=3, NM=0 (32 bits)
Emif1Regs.SDRAM_CR.all = 0x00000721;

    But, without using the pins EM1A11 and EM1A10, how should I configure this register?

  • 0 in reply to Clecio Jung
    TI__Mastermind 30185 points

    Hi Clecio,

    I don't think there would be any change in the configuration of the register when there are unused address lines, however any time you access memory using the EMIF you will just need to be conscious that you have limited address access, that way you don't accidentally try to use those address pins when they're not available. This would be more of a software implementation of making sure you don't try to access memory out-of-bounds for the address lines you have available.

    Also, regarding your question on the PRE command, since our primary expert is out I found this article online which explains the use of precharging, it does look like this is required (at least from my understanding, but you can see if these apply to your use case):

    https://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/3

    https://electronics.stackexchange.com/questions/246835/what-is-the-need-for-precharging-in-sram-dram-memory-cell

  • 0 in reply to Omer Amir
    TI__Guru**** 193086 points

    Hi Clecio,

    1. The SDRAM is organized into banks, and bank is further divided into pages. Only one page per bank can be opened at a time. If a page in a particular bank is already open, you cannot open another page within the same bank without closing the currently open page. The EMIF controller can issue PRE command to close the open page (or open row) in a specified bank or the open row in all banks simultaneously. The A10 determines whether one or all banks are to be pre-charged. How is A10 pin of SDRAM device connected?  

    2. The row address (A10 and A11) are sampled to select ROW during ACTV command, and A0~A8 (with A10 defining the auto precharge) define the starting column address and signal the SDRAM memory to begin RED or WRITE operation. If A10 and A11 are not connected, how does EMIF controller selects the page without row address?

  • 0 in reply to Omer Amir
    Prodigy 20 points

    Hi Omer.

    Those articles are very interesting, and I agree with you, it seems that precharging is required.

    Thanks.

  • 0 in reply to QJ Wang
    Prodigy 20 points

    Hi Wang.

    Pin A10 and A11 of the SDRAM IC are both connected to GND.

  • 0 in reply to Clecio Jung
    TI__Guru**** 193086 points

    Hi Clecio,

    You can still use the SDRAM with limited space (A10=A11=0). The auto-refresh is disabled (A10=0), and only ROW 0 (A10=A11=0) of the selected bank can be precharged, activated, read from and written to.

  • 0 in reply to QJ Wang
    Prodigy 20 points

    Hi Wang. That's good news. But what I failed to understand is how to configure the EMIF driver so that I can use in the way you suggested. The register CR (SDRAM_CR) is configured in the same way? There is any other register whose configuration I need to change? And how do I make sure that the driver keep the pins A10 and A11 always low? Is it by restricting the addresses used?

  • 0 in reply to Clecio Jung
    TI__Guru**** 193086 points

    Hi Clecio,

    Clecio Jung said:
    The register CR (SDRAM_CR) is configured in the same way?

    # of banks and page size are the same.

    Clecio Jung said:
    There is any other register whose configuration I need to change?

    I don't think so.

    Clecio Jung said:
    And how do I make sure that the driver keep the pins A10 and A11 always low?

    To use the whole memory range, you can use a multiplexer to route A10 and A11 to different devices (AS4C8M32S-6, and others), and use a GPIO to select the device.  

    Clecio Jung said:
    Is it by restricting the addresses used?

    If A10=A11=0, only limited memory range can be used.