TMS320F280049C: Cycle-by-Cycle High and Low Comparator Usage

Hi, 

Ahmet Talha Dudak said:

Is it not possible for low and high comparator to work at the same time ?

This is possible.

How have you configured your outputs to be pinned out from the device? Are you using the output XBAR? 

Best Regards,

Ben Collier

Hi,

CMPSS Mux is configured as HPMXSEL=0 and LPMXSEL=0. I am not using the output X-BAR. The output of CMPSS is TRIP5 and TRIP7. TRIP5 is for High comparator. TRIP7 is for low comparator. They are linked to DCBH with combinational trip. The output of the low comparator is inverted and the outputs of the comparators is triggered with rising edge(DCxH HIGH). Asynchronous paths is enable in CMPSS. High comparator works during 10ms. Then low comparator works during 10ms. This scenario repeats itself over and over again.

Thanks,

Hi Ahmet,

The CMPSSn low side DAC output inversion does seem to cause odd behavior in ePWM module combination MUX trips being cleared or set.

Noted the low side trip behaves as expected when set (trip high or low) ePWM-B action qualifier. Oddly the low side action qualifier ePWM-B (CMPSSn latched or CBC) randomly refuses to clear.  You may notice latch up CCS debug probe (register view) if action qualifier B is set (trip high) combination MUX settings. At times clearing the fault flags does not seem to work, reset MCU clears the flags. 

BTW: Be sure the CMPSSn GPIO inputs are set asynchronous and they will toggle 10ms perhaps even synchronously at times. 

Ahmet,

Can you please attach your initialization code for the comparator?

void setupPCMCCMPSS(void)

{

CMPSS_enableModule(CMPSS6_BASE); CMPSS_enableModule(CMPSS5_BASE); CMPSS_configHighComparator(CMPSS6_BASE,CMPSS_INSRC_DAC);

CMPSS_configHighComparator(CMPSS5_BASE,CMPSS_INSRC_DAC);

CMPSS_configLowComparator(CMPSS6_BASE,CMPSS_INSRC_DAC | CMPSS_INV_INVERTED ); CMPSS_configLowComparator(CMPSS5_BASE,CMPSS_INSRC_DAC | CMPSS_INV_INVERTED ); ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_6, 0);

ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_5, 0);

ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_6, 0);

ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_5, 0);

CMPSS_configDAC(CMPSS6_BASE,(CMPSS_DACVAL_PWMSYNC | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW)); CMPSS_configDAC(CMPSS5_BASE,(CMPSS_DACVAL_PWMSYNC | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW));

EALLOW;

CMPSS_configureSyncSource(CMPSS6_BASE, 2);

CMPSS_configureSyncSource(CMPSS5_BASE, 3);

EDIS;

CMPSS_setDACValueHigh(CMPSS6_BASE,4096);

CMPSS_setDACValueHigh(CMPSS5_BASE,4096);

CMPSS_setDACValueLow(CMPSS6_BASE,0);

CMPSS_setDACValueLow(CMPSS5_BASE,0);

CMPSS_configOutputsHigh(CMPSS6_BASE, CMPSS_TRIP_ASYNC_COMP);

CMPSS_configOutputsHigh(CMPSS5_BASE, CMPSS_TRIP_ASYNC_COMP);

CMPSS_configOutputsLow(CMPSS6_BASE, CMPSS_TRIP_ASYNC_COMP);

CMPSS_configOutputsLow(CMPSS5_BASE, CMPSS_TRIP_ASYNC_COMP);

CMPSS_clearFilterLatchHigh(CMPSS6_BASE);

CMPSS_clearFilterLatchHigh(CMPSS5_BASE);

CMPSS_clearFilterLatchLow(CMPSS6_BASE);

CMPSS_clearFilterLatchLow(CMPSS5_BASE);

}

Good to hear it works High & Low combination ePWM-B, very strange behavior though.