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TMS320F280049C: TM320F280049C and CLB

TI-CSC
Genius 11480 points
Part Number: TMS320F280049C

Hello E2E Experts,

Good day.

 I like to use the CLB function of the TMS320F280049C microcontroller in my application. After reviewing the device TRM and other provided documents by TI, I have some questions regarding the CLB functionality of our device.

1. Correct me if I'm wrong, but I believe the device has 4 tiles in the CLB subsystems (page 2822 of SPRUI33G document, section 29.2, line 1) and they are named CLB1, CLB2, CLB3, and CLB4. (that naming comes from page 2860 of SPRUI33G document, table 29-17 base address of the registers). So there is no CLBxTILEn (x is the CLB module number and n is the tile number) and CLBx refers to TILE x of the CLB module.

2. I'm confused how the output of the TILES. On page 2833 of the SPRUI33G document, Fig 29-8, it shows that there are 24 outputs (OUT0 - OUT23) for each TILE that are provided by replicating the 7 boundary outputs of the TILE. However, on page 2848 of the SPRUI33G document, Fig 29-18 shows 32 outputs. Which one is currect? Also, in the same figure, what is the CLB_OUT4_2 signal?

3. On page 2834 of the SPRUI33G document, Table 29-4, the output signal multiplexer is described. However, on page 6 of the SPRACY3 documents, Table 3-2 different destinations are mentioned for some of the outputs. Also, in the same table, names such as CLB1_OUT0_0 are not clear to me.

4. On page 2834 of the SPRUI33G document, Table 29-4, it is mentioned that it is possible to override EPWM1A_AQ with OUTLUT4 of CLB1. While I know where that signal is in Fig 18-20 (on page 1918 of the SPRUI33G document), I'm having a hard time understanding its performance. I know it is a general question, but can you explain how the value of 1 or 0 of this signal can change the output of the corresponding ePWM?

5. Where is the EPWMx_OE signal? can you refer me to a figure that shows this signal and where it connects to?

Regards,

TI-CSC

  • 0
    TI__Mastermind 22290 points

    1. This is correct

    2. There are 24 outputs, on each TILE, we will remove any references indicating there are 32 outputs in the next revision of the TRM.

    3. Can you share a link to the SPRACY3 document? Is this the TRM or datasheet for some other device?

    4. The EPWM has several stages before the final output is produced such as the Action Qualifier stage, Deadband stage, Trip Zone stage, etc. If you want to swap the output of one of these stages (such as the output of the action qualifier module) with a CLB output, you can do this via the output override function.

    5. EPWMx_OE refers to the output of the trip-zone module.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    TI__Genius 11480 points

    Hello Luke,

    Good day.

    Luke Jones said:
    Can you share a link to the SPRACY3 document? Is this the TRM or datasheet for some other device?

    SPRACY3 is an application note (Achieve Delayed Protection for Three-Level Inverter With CLB) here is the link to it: https://www.ti.com/lit/pdf/spracy3

    The original question is:

    TI-CSC said:
    On page 2834 of the SPRUI33G document, Table 29-4, the output signal multiplexer is described. However, on page 6 of the SPRACY3 documents, Table 3-2 different destinations are mentioned for some of the outputs. Also, in the same table, names such as CLB1_OUT0_0 are not clear to me

    Thank you in advance.

    Regards,

    TI-CSC

  • 0 in reply to TI-CSC
    TI__Mastermind 22290 points

    Hi TI-CSC,

    CLB1_OUT0_0 is equivalent with CLB1_OUT0. CLB1_OUT0_1 is equivalent to CLB1_OUT8. This is because the outputs of the 8 OUTLUTs, are repeated 2 times to create 24 outputs total per CLB tile.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    TI__Genius 11480 points

    Hello Luke,

    Good day.

    Thank you for all your input.

    Regarding enabling CLB output, on page 2834 of SPRUI33G document (TRM), Table 29.4, it is mentioned that it is possible to override the listed peripheral signals with CLB outputs. In the table, it is mentioned that CLB outputs 12 and 13 are connected to "All XBARs".

    1) Does "XBAR" refer to INPUTXBAR of the crossbar? please provide more details.

    2) Are all CLB OUTs connected to All XBARs or some outputs are only connected to specific XBAR signals?

    Regards,

    TI-CSC

  • 0 in reply to TI-CSC
    TI__Mastermind 22290 points

    Hi TI-CSC,

    Specific CLB outputs are connected to the EPWM XBAR, CLB XBAR, and Output XBAR. Since INPUTXBAR is not included, I've updated this table to simply say XBARs in the next release of the TRM. You can refer to the XBAR chapter to see which CLB outputs are connected to the XBARs.

    Thank you,

    Luke