• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 82 subscribers
  • Views 196 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMDSCNCD28P65X: TMDSCNCD28P65X: Can't debug on CCS 12.8.1

Jerry Lin
Prodigy 30 points
Part Number: TMDSCNCD28P65X
Other Parts Discussed in Thread: C2000WARE, UNIFLASH

Tool/software:

Hi TI team,

I'm studying the TMDSCNCD28P65X control card and trying to program some example code from C2000Ware_5_04_00_00 using CCS version is 12.8.1.00005

I've imported the example project: gpio_ex1_setup. And it build successfully. 

But I can't load it successfully. The CCS log are shown below:

""""""""

C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected flash banks are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU1: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU2: GEL Output:

RAM initialization done

C28xx_CPU2: GEL Output:
Memory Map Initialization Complete
C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected flash banks are programmed.
C28xx_CPU2: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU2: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
C28xx_CPU2: File Loader: Verification failed: Values at address 0x00A800@Program do not match Please verify target memory and memory map.
C28xx_CPU2: GEL: File: D:\Project\Tesseract\TI P65 test\gpio_ex1_setup\CPU1_RAM\gpio_ex1_setup.out: a data verification error occurred, file load failed.

""""""""

However, I can load & verify FW by using UniFlash. (Version 8.8.1.4983)

Can someone please help to check and how to solve it?

Why the CCS cannot debug & load FW?

Thanks.

  • 0
    TI__Mastermind 21656 points

    Hi Jerry, 

    Jerry Lin said:
    C28xx_CPU2: File Loader: Verification failed: Values at address 0x00A800@Program do not match Please verify target memory and memory map.
    C28xx_CPU2: GEL: File: D:\Project\Tesseract\TI P65 test\gpio_ex1_setup\CPU1_RAM\gpio_ex1_setup.out: a data verification error occurred, file load failed.

    The target configuration file seems to be trying to load to CPU2. Is this what you're trying to achieve? 

    Can you double check the target configuration file settings? Ensure this is set to Active.You can right click on this .ccxml, then "Set to as Active Target Configuration".

    Double check the debug configurations by going to the following setting.

    Go to Debug Configuraitons...

    Under the "Program" Tab, ensure that the correct program is being loaded for CPU1.

    CPU2, should not be filled

    Then click on the bug icon, and try and debug your application again

    Best regards, 

    Ryan Ma

  • 0 in reply to Ryan Ma
    Prodigy 30 points

    Hi Ryan

    Thanks for your reply.

    I've set it as Active Target Configuration.



    And the debug configurations setting are the same as yours.

    But it still has same failure.

    Are there any other settings that I need to check?

    Best regards.

    Jerry

  • 0 in reply to Jerry Lin
    TI__Mastermind 21656 points

    Hi Jerry,

    Under the following red box, can you check CPU2's settings. Make sure there is no program there unless you have specified some program specifically for CPU2.

    Best,

    Ryan Ma

  • 0 in reply to Ryan Ma
    Prodigy 30 points

    Hi Ryan

    I've followed the CPU2's setting as below. (Only loaded for CPU1) And seems can be loaded into chip.

       

    And the log is shown below:

    '''''''''''

    C28xx_CPU1: GEL Output:
    Memory Map Initialization Complete
    C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
    C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
    C28xx_CPU1: GEL Output:
    CPU2 is out of reset and configured to wait boot.
    (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
    C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected flash banks are programmed.
    C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
    C28xx_CPU1: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
    C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
    C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
    C28xx_CPU1: GEL Output:
    CPU2 is out of reset and configured to wait boot.
    (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
    C28xx_CPU2: GEL Output:

    RAM initialization done

    C28xx_CPU2: GEL Output:
    Memory Map Initialization Complete
    C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected flash banks are programmed.
    C28xx_CPU2: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
    C28xx_CPU2: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)

    '''''''''''

    But when I try to run the Debug, it will always jump to ESTOP0.

    Are there any other settings that I need to check?

    Best regards.

    Jerry

  • 0 in reply to Jerry Lin
    TI__Mastermind 21656 points
    Jerry Lin said:

    But when I try to run the Debug, it will always jump to ESTOP0.

    Hi Jerry, 

    Did you add the ESTOP0? this is the software breakpoint and will halt the cpu when debugger is connected. In the original example there is no ESTOP0.

    Can you remove that ESTOP0 if you would not want the CPU to halt, instead keep the empty while loop.

    Best,

    Ryan Ma

  • 0 in reply to Ryan Ma
    Prodigy 30 points

    Hi Ryan,

    This project was from the original C2000Ware example. I didn't modify any code.

    However, once I've load the correct FW, it won't stuck at the ESTOP0. I think I might make a mistake about debug target.

    And like you said, only load FW to CPU1. CPU2 stays empty, then this example code can be execute.

    Thanks for your help.

    Best regards.

    Jerry