• State Resolved
  • Locked Locked
  • Replies 16 replies
  • Answers 1 answer
  • Subscribers 86 subscribers
  • Views 525 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F2812: External ADC SoC input for TMS320F2812

Anuradha Ogale
Prodigy 20 points
Part Number: TMS320F2812


Tool/software:

I am working on TI’s TMS320F2812 uC, and have a question regarding external ADC SoC trigger on pin GPIOE1_XINT2_ADCSOC.

 

I have the input signal coming in on this pin as a positive pulse, when I wish to trigger ADC conversion. However, I observed that the actual sampling starts after falling edge of the positive pulse on this pin. I am thus thinking of making this input signal active low. Instead of a pulse, can I just set it low when I wish to start ADC conversion, and keep it otherwise high at all times? Or the pin does need to see a positive pulse of certain width before triggering SoC on its falling edge?

 

Below are some of the timing diagrams I found from datasheet and reference guide- it always shows a pulse for SoC trigger.

  • 0
    TI__Mastermind 36526 points

    Hi,

    Anuradha Ogale said:
    Or the pin does need to see a positive pulse of certain width before triggering SoC on its falling edge?

    Yes, this is the case. The positive pulse should be at least 1 ADC clock cycle. 

    Best Regards,

    Ben Collier

  • 0 in reply to Benjamin Collier
    Prodigy 20 points

    Thanks- could you also confirm whether when the actual sampling starts is dependent on falling edge or rising edge of the trigger pulse? 

  • +1 in reply to Anuradha Ogale
    TI__Mastermind 36526 points

    Hi,

    So this delay will be dependent on ADC Clock. It will be from the first ADC Clock falling edge (when the external signal is high) to the third subsequent ADC Clock rising edge. 

    This is how the 2.5 ADC clocks is reached in the above graph. 

    Best Regards,

    Ben Collier

  • 0 in reply to Anuradha Ogale
    TI__Mastermind 36526 points

    Hi,

    I apologize, my above response was inaccurate. I have corrected it. 

    Best Regards,

    Ben Collier

  • 0 in reply to Benjamin Collier
    Prodigy 20 points

    Hi- I still see the old response-

  • +1 in reply to Anuradha Ogale
    Prodigy 20 points

    Okay, I now see the updated response. Yes, the 2 ADC clock cycle delay of td(SH) is shown in the datasheet. What was not clear to me from datasheet was what the additional half ADC clock cycle delay is dependent on: from your explanation it seems to me that it will be minimum of half ADC clock cycle and maximum of 1.5 ADC clock cycles after falling edge of ADC clock, once SOC trigger input goes high. Is that correct?

  • 0 in reply to Anuradha Ogale
    TI__Genius 14755 points

    Hey Ben,

    I just reached out over email but also wanted to comment on this thread for reference; can you please help to answer Anu's latest question?

    -Matt

  • 0 in reply to Matt Calvo
    TI__Mastermind 36526 points

    Sorry, these threads get closed when the resolved button is clicked.

    Anuradha Ogale said:
    it will be minimum of half ADC clock cycle and maximum of 1.5 ADC clock cycles after falling edge of ADC clock, once SOC trigger input goes high. Is that correct?

    After falling edge of ADC clock, it will be 2.5 ADC clock cycles until the sample and hold begins. 

  • 0 in reply to Benjamin Collier
    TI__Genius 14755 points

    No worries at all Ben; thank you so much for following back up on this and clarifying the clock cycle interpretation! :) 

    -Matt

  • 0 in reply to Benjamin Collier
    Prodigy 20 points

    Hi Ben, I would rephrase my question as follows: from the instant SOC trigger input goes high, to the instant where sample and hold begins, the minimum time it will take would be 2.5 ADC clock cycles. But depending on where in ADC clock cycle the SOC trigger input went high, it could also go upto 3.5 ADC clock cycles?

  • 0 in reply to Anuradha Ogale
    TI__Mastermind 24360 points

    Hi Anu,

    Ben is out of office for the next week, so please expect a delay in response until his return. Thanks for your patience!

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Genius 14755 points

    Thank you for the heads up Allison!

    With Ben being OOO, is there anyone else within the C2000 Apps team that we can loop in for the time being to help address Anu's latest question? 

    We are just looking for confirmation of the ADC clock cycle interpretation so hopefully someone within Apps or Systems would be able to quickly confirm this.

    -Matt

  • 0 in reply to Matt Calvo
    TI__Guru* 81490 points

    I believe the issue here is the interpretation of the signal graph.  This trigger pulse is coming from outside the ADC domain, either from the EV module, SW, or ext GPIO pin.

    In any case all of these signals are in the SYSCLK domain(likely 150MHz).  Once these are presented to the ADC clock, it will be latched on the next rising edge, and then be cleared and take the cycles shown.

    For an external signal this simply needs to meet the GPIO qualification requirements(dependent on how the GPIO is configured, either SYNC or with a qualification time).  The internal logic will take care of holding the signal until it is latched by the ADC, regardless of the source.  I would not use ASYNC mode on the GPIO input here as it will further complicate things in terms of latching this signal.

    Anuradha Ogale said:
    Hi Ben, I would rephrase my question as follows: from the instant SOC trigger input goes high, to the instant where sample and hold begins, the minimum time it will take would be 2.5 ADC clock cycles. But depending on where in ADC clock cycle the SOC trigger input went high, it could also go upto 3.5 ADC clock cycles?

    This is correct, worst case the trigger comes right after a rising edge of ADC clock, so it will take an additional ADC clock(3.5 total) before the signal gets latched into the ADC.  Best case it comes right before a rising edge an we get 2.5 ADC shown.  

    I think Ben has clarified this, but from an external signal POV it is a rising edge triggered event, again from the GPIO setting, the diagram is showing from the falling edge of the latched signal presented to the ADC, likely to give some indication of the above(but I agree this diagram could be more clear).

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 20 points

    Thank you for clarifying. 

    "Once these are presented to the ADC clock, it will be latched on the next rising edge, and then be cleared and take the cycles shown.....The internal logic will take care of holding the signal until it is latched by the ADC, regardless of the source. "

    I have a follow up question on above behavior: If the external trigger signal is held high longer than the instant where internal logic clears the latched signal presented to ADC, will it detect the high state of external trigger signal as a second trigger? Does this mean that it'd be better to set external trigger signal pulse width to just one ADC clock cycle and nothing more than that? 

  • +1 in reply to Anuradha Ogale
    TI__Guru* 81490 points
    Anuradha Ogale said:
    If the external trigger signal is held high longer than the instant where internal logic clears the latched signal presented to ADC, will it detect the high state of external trigger signal as a second trigger? Does this mean that it'd be better to set external trigger signal pulse width to just one ADC clock cycle and nothing more than that? 

    Great question, the logic involved is edge based, so this will not be a concern.  Unless the signal transitions back to low, a new trigger will not be generated even if the line stays high past the qualification of the signal.

    Best,

    Matthew