Tool/software:
I'm currently trying to determine the maximum achievable SPI clock speeds for both High-Speed mode and normal SPI mode on the TMS320F28388D.
In a referenced forum post, it was stated that the maximum SPI frequency in High-Speed mode is 50 MHz, while in normal mode it is 12.5 MHz.
Based on my research, I found that the SPI clock is derived as:
SPI Clock = LSPCLK / 4 (minimum divider)
With LSPCLK = SYSCLK = 200 MHz, this would indeed result in 50 MHz – which aligns with the stated maximum for High-Speed mode.
This raises two questions:
1. Regarding SPI High-Speed Mode:
Does achieving the 50 MHz clock require setting LSPCLK equal to SYSCLK?
If so, this would affect other LSPCLK-dependent peripherals (like additional SPI modules or McBSP).
Would that be a problem, or is it acceptable since I can still individually configure the SPI baud rate using the SPIBRR register?
2. Regarding normal SPI (non-High-Speed mode):
It was mentioned that the maximum frequency is 12.5 MHz.
Assuming the same LSPCLK / 4 rule, this implies LSPCLK = 50 MHz in that case.
Does this mean the 12.5 MHz limit is not absolute, but simply based on that specific LSPCLK example?
In other words, if I increase LSPCLK, would the normal SPI (without High-Speed mode) support higher SPI clock rates, up to the divider limit?
If this would be the case I can not see the difference between the normal SPI and the SPI in High-Speed Mode.
Below are the relevant excerpts I found in the Technical Reference Manual (TRM):
Best regards,
Wilko
