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TMS320F280049: FSI interface clarification

Dan Abbey
Prodigy 590 points
Part Number: TMS320F280049

Hi Team, 

I'm working with a customer on an application where they are considering ~5x devices to be daisy chained together via FSI interface.  They have some questions on what happens under certain conditions, could you please help with the below? 

We have been studying the Technical Reference Manual (SPRUI33C) and have some elaborate questions we hope You can find some answers to.

1: Given the FSI-RX is idle (after a frame-end with no errors, waiting for a frame-start).

  1. Will the receiver be disrupted by a flush sequence, or will it be OK?
  2. What happens if data are sampled, but they do not match “frame-start”?
    Will the receiver detect a frame start, when it occurs later on in the bit stream?
  3. What happens if a noisy/invalid clock appears, but data are all zeros?

2: Given the FSI-RX is receiving/decoding mode (a frame-start was detected)

  1. Will invalid data sampled during any part of the frame (type, tag, data, crc etc.) bring the receiver in a unrecoverable state, where a soft-reset is required to recover normal operation (clock signal is valid)?

3: Will the “RX_VIS_1.RX_CORE_STS” always flag an error when the FSI_RX ended up in an unrecoverable state, no matter what was the cause of error?

4: In chapter 28.4.3.10, there is a section with ambiguous wording:

“Ensure that the clock and data lines satisfy the Electrical Characteristics and timing requirements of the FSI module found in the data manual for this device. Failure to do so may cause the receiver state machine to go into an unrecoverable error state. The receiver can only be recovered by undergoing a soft reset.”

Right after mentioning an unrecoverable error state, the manual describes the soft reset recovery.

Will a soft reset ALWAYS recover any possible error state, or is there a chance the FSI receiver can end up in a truly unrecoverable situation?

 Thanks 

Dan

  • 0
    TI__Mastermind 42906 points

    Hi Dan,

    Taking these questions offline.

    Dan Abbey said:

    2: Given the FSI-RX is receiving/decoding mode (a frame-start was detected)

    1. Will invalid data sampled during any part of the frame (type, tag, data, crc etc.) bring the receiver in a unrecoverable state, where a soft-reset is required to recover normal operation (clock signal is valid)?

    These cases are are all documented in the TRM section 28.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset

    Dan Abbey said:
    3: Will the “RX_VIS_1.RX_CORE_STS” always flag an error when the FSI_RX ended up in an unrecoverable state, no matter what was the cause of error?

    This is documented in the RX_CORE_STS register bit description (Table 28-43)

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    TI__Mastermind 42906 points

    Providing missing answers to questions:

    Dan Abbey said:

    1: Given the FSI-RX is idle (after a frame-end with no errors, waiting for a frame-start).

    1. Will the receiver be disrupted by a flush sequence, or will it be OK?

    FSI receiver will be unaffected by any number of flush sequences.

    Dan Abbey said:
    What happens if data are sampled, but they do not match “frame-start”?
    Will the receiver detect a frame start, when it occurs later on in the bit stream?

    The receiver will look for a bit pattern that matches the SoF (start of frame). Whenever it sees 1001 (SoF pattern) it will assume it’s receiving a frame and expect the correct frame structure. Errors will likely occur if arbitrary bit patterns are on the FSI lines.

    Dan Abbey said:
    What happens if a noisy/invalid clock appears, but data are all zeros?

    This can cause the receiver to go to an invalid state. This issue is detectable if PING and FRAME watchdog timers are configured. If the receiver goes into one of these error states it will need to be reset.

    Dan Abbey said:

    2: Given the FSI-RX is receiving/decoding mode (a frame-start was detected)

    1. Will invalid data sampled during any part of the frame (type, tag, data, crc etc.) bring the receiver in a unrecoverable state, where a soft-reset is required to recover normal operation (clock signal is valid)?

    Documented in TRM section 28.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset

    Dan Abbey said:
    3: Will the “RX_VIS_1.RX_CORE_STS” always flag an error when the FSI_RX ended up in an unrecoverable state, no matter what was the cause of error?

    Documented in TRM RX_CORE_STS register bit description. RX_VIS_1.RX_CORE_STS  being 1 is indicative of an error condition. The receiver also generates the other error conditions like TYPE_ERROR etc. 

    Dan Abbey said:

    4: In chapter 28.4.3.10, there is a section with ambiguous wording:

    “Ensure that the clock and data lines satisfy the Electrical Characteristics and timing requirements of the FSI module found in the data manual for this device. Failure to do so may cause the receiver state machine to go into an unrecoverable error state. The receiver can only be recovered by undergoing a soft reset.”

    Right after mentioning an unrecoverable error state, the manual describes the soft reset recovery.

    Will a soft reset ALWAYS recover any possible error state, or is there a chance the FSI receiver can end up in a truly unrecoverable situation?

    A proper reset and re-sync will recover the FSI receiver when it’s in an error state. When resetting the receiver it must see a FLUSH sequence on its pins to come out of reset and re-synchronize.

    Best,

    Kevin