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TMS320F280049: TIDM-02002-software for PWM modulation and active synchronous rectifiction

huijin Wang
Intellectual 270 points
Part Number: TMS320F280049

Dear Ms. / Mr.

I am studying the software project "clllc_28004x" which is about Bidirectional CLLLC Resonant Dual Active Bridge (DAB) and I have some questions:

1. When power flows from primary side to secondary side, the PWMs for the primary side are generated around the period of the TB counter, when the power flows from the secondary side to the primary side, the PWMs for the secondary side are generated around the period of the counter, am I right? but the figure 25 in the user guide seems not like this, its around zero of the TB counter.

2. According to the user guide, there is a phase-shift between the PWM TB bases for the primary side and secondary side because of the propagation delay of the PWMs for the secondary side.

I checked the code about the calculation for the TBPHS for the secondary side, but I can not understand what it mean, could you please give a more detail explanation about the formulas for two directions:

  • the formula includes 3 parts, what do the 3 parts represent?
  • and why is CLLLC_pwmphaseshiftPrimSec_ns  81 ?
  • when power flows from primary to secondary, the rising edge for the secondary side should align with the PWM rising edge of the primary side, right? But it is generated on the point of CTR =0 or CTR=PRD,does this mean the rising edge generated at this point will align with the PWM for the primary side after the propagation delay?
  • if there is no propagation delay, the phase shift is in no need anymore, I can just link the SEC-LEG1 CMPA with PRIM-LEG1-CMPA, and use the TZ to control the falling edge, is this ok? 
  • from my understanding, the falling edge for the secondary side is triped when the current reached 0. But when we test the current is 0, with the propagation, I think the PWM will be delayed? How to solve this?

  • 0
    TI__Mastermind 43730 points

    1. The goal for the reverse power flow will be to exactly swap the PWM action. This is what is shown in the image above. Please note only LEG1 is shown in the image above and LEG 2 will be centered around period in reverse mode. I do not think choosing one was or the other will impact the design.

    huijin Wang said:
    the formula includes 3 parts, what do the 3 parts represent?
    huijin Wang said:
    and why is CLLLC_pwmphaseshiftPrimSec_ns  81 ?

    a. Because the blanking edge can be placed at zero and period, we shift the time base by period ticks / 2 

     b. 81ns is the emperical number tuned on the power stage.  

     c. this shift by 2, is explained in the code comments, please refer to those. 

    huijin Wang said:
    if there is no propagation delay, the phase shift is in no need anymore, I can just link the SEC-LEG1 CMPA with PRIM-LEG1-CMPA, and use the TZ to control the falling edge, is this ok? 

    No not true, because we need to add blanking we need to shift the time base of the sec PWM such that the zero aligns with where we want the blanking pulse to be i.e. the prim rising edge

    huijin Wang said:
    from my understanding, the falling edge for the secondary side is triped when the current reached 0. But when we test the current is 0, with the propagation, I think the PWM will be delayed? How to solve this?

    This is the advantage we have with programmable CMPSS, you can program a higher threshold i.e. 0.1 or 0.2 Amps to trigger the PWM trip. 

    huijin Wang said:
    when power flows from primary to secondary, the rising edge for the secondary side should align with the PWM rising edge of the primary side, right? But it is generated on the point of CTR =0 or CTR=PRD,does this mean the rising edge generated at this point will align with the PWM for the primary side after the propagation delay?

    Please refer to the diagram for this understanding. 

  • 0 in reply to Manish Bhardwaj
    Intellectual 270 points

    According to the Fig.24 , for the active synchronous rectification, xA set high at CTR=0, and  is tripped when Time base is counting up, and xB is set at CTR=PRD and is  tripped when Time Base is counting down, but in the code, when the power flows from primary to  the secondary side, xA is tripped when TB is counting down and xB is tripped when TB is counting up.

  • 0 in reply to huijin Wang
    Intellectual 270 points

    I found that when power flows to the secondary, PWMs for SEC-LEG1 are swapped, I think this is the key.