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TMS320F28374S: An ePWM channel jitters from time to time when running on the CLA

Justin Ryu1
Prodigy 60 points
Part Number: TMS320F28374S

Condition

  • ePWM triggers ADC sampling
  • At the end of the ADC ISR, CLA task1 is triggered by SW
  • In the CLA, an inline function is called from a header file, and the following PWMs duty cycles are set
    • Using up-down counter
    • PWM2A
      • Using only Comp A 
      • HIGH on up, LOW on down
      • Duty cycle of PWM2A changes every switching cycle.
    • PWM3A
      • Using Comp A and B
      • Comp B is synchronized with Comp A of PWM2A
      • Comp A is fixed count which is greater than 0 PWM count number
    • In summary, PWM3A is leading over PWM2A. Falling edge of PWM3A coincides to the rising edge of PWM2A 

Problem

  • Sometimes PWM2A and PWM3A does not coincide. Most of the time, they coincide. 

Observation

  • Moving the exactly same code to run on the CPU1, the problem disappeared.

Is there anything that I can try to resolve this issue?

  • 0
    Prodigy 60 points

    To be precise, PWM3A and PWM2A are out of sync in the range of +/-80ns. Sysclk frequency is 100MHz, so it seems that out of sync happens between 0 to 8 sysclk cycles. 

  • 0 in reply to Justin Ryu1
    TI__Mastermind 23740 points

    Hi Justin,

    Have you tried to map when the CLA task starts and ends? Are you using any shadow loading or are you using immediate mode? 

    Justin Ryu1 said:
    Moving the exactly same code to run on the CPU1

    Does this mean you update the epwm configuration values within the ADC ISR or within an EPWM ISR? 

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 60 points

    Hi Marlyn,

    I am using shadow loading. I only have ADC ISR which also triggers CLA at the end of the loop. However, yes, the epwm configuration values are updated in the ADC ISR.

    Marlyn Rosales Castaneda20 said:
    Have you tried to map when the CLA task starts and ends?

    What do you mean by that?

    Thanks,

    Justin

  • 0 in reply to Justin Ryu1
    TI__Mastermind 23740 points

    Justin,

    The period, compare, and phase registers should be updated at a known good point in the switching cycle. One suggestion is to write the new PWM register values to dummy variables first, within the CLA task. Once new register values are calculated and written to dummy variables, the PWM ISR should be enabled. The PWM ISR will then trigger at a known good point in the cycle. PWM ISR can be disabled from within the ISR at the end of its code. 

    What I had meant by map the CLA task was to possibly toggle a gpio at the beginning and end of the task and see how that lines up with your epwm output. 

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    TI__Mastermind 23740 points

    This thread was resolved offline. Below is the resolution:

    The root cause for the observed jitter was the distribution of updates to EPWM2A and EPWM3A across different PWM cycles in some cases resulting in to the misalignment of the edges. As the execution time of ADC ISR surpasses the boundary point (TBCTR = 0) so there is a possibility that write to EPWM2A happens before the boundary while writes to EPWM3A happens after the boundary. In that case, the new shadow value will loaded to the active register for EPWM2A at TBCTR=0 while EPWM3A will still contain the older value resulting into the inconsistency between the two. 

    To avoid this issue, the key idea is that writes for both EPWM2A and EPWM3A need to be scheduled in the same PWM cycle. This could be done by triggering the ADC ISR early (if that’s allowed by the system) so that it finishes the execution before the boundary. Or the other way could be by offloading some part of the code to CLA for faster execution or by reshuffling the sequence of routines inside the ISR.

    Best Regards,

    Marlyn