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# What is the conversion time for the SD24_B in the MSP430F6736?

Other Parts Discussed in Thread: MSP430F6736

What is tCONVERT (conversion time) for the SD24_B in the MSP430F6736?  I see this specified for the 10-Bit ADC but not for the 24-Bit Sigma-Delta ADC.

I searched through our datasheets, and I had no success finding any sigma-delta ADC conversion time for any of these peripherals:

• SD14
• SD16_A
• SD24
• SD24_A
• SD24_B

When I try to calculate the conversion time myself, I get 3.2 ms, which seems long.  I would like someone to verify my calculations (no longer attached.  Updated version in later post).

If SMCLK is used for the SD24_B, does this mean I cannot use LPM3 during the conversion time?

References:
Datasheet MSP430F673x, MSP430F672x Mixed Signal Microcontroller
Find, "Tconvert"
Find, “Differential input voltage for specified”

MSP430x5xx and MSP430x6xx Family User's Guide
Find, “The maximum modulator frequency”
Find, “~1.2V from shared REF”
Find, “SD24_B Converter x Oversampling Control Register”

SD16_A on F2013 timings
SD24_A Conversion time

• Hi Jason,

Let me dig into this for you.  Basically OSR will impact the conversion time, but I will try to get a formula for you.

Alan

• Hey Jason,

Generally, a way to calculate the sampling time is to take your SD_24 frequency and divide that by your OSR to get the sampling rate. The inverse of this would obviously be your sampling time. Basically, the SD_24 takes many samples (in this case 256), and then averages them to get a better SNR on the data. Then the digital filter rids the samples of this noise, giving you the final result from the SD_24.

Firstoff, I can confirm your calculations, yes 3.2ms would be correct for the sampling time based on the parameters you sent me. Your sampling rate seems pretty slow. Most of the times this speed is around 1MHz, which allows for the oversampling without taking too long.

Secondly, yes, if you are planning on using SMCLK for your SD_24 clock, you will not be able to use LPM3. This is all defined within the datasheet, as you most certainly know. The only option that would be available would be to use ACLK. This is the only clock that remains active in LPM3.

Let me know if you have any more questions.

• Tyler Witt said:
Secondly, yes, if you are planning on using SMCLK for your SD_24 clock, you will not be able to use LPM3. This is all defined within the datasheet, as you most certainly know. The only option that would be available would be to use ACLK. This is the only clock that remains active in LPM3.

I think that on 5xx/6xx parts if you have the SMCLK request enable set in the UCS module (which it does by default) then you can go to "LPM3" with SMCLK still enabled (but of course you will have higher current consumption). It won't be true LPM3 because SMCLK is still on. See the 5xx user's guide table 5-1 on p. 167.

What I'm unsure of is if while you enter LPM3, with the SD24 requesting SMCLK and the SMCLKREQEN set, I'm unsure if SMCLK will only output until SD24 is done with the conversion, or if it will always be output (basically LPM0). You might have to try that out.

Regards,

Katie

• Katie Enderle Pier said:
I'm unsure if SMCLK will only output until SD24 is done with the conversion, or if it will always be output (basically LPM0).

Well, since you usually want to do something with the sampled value, you'll already come out of LPM when the SD24 is done. You can then disable the SD24 completely and enter real LPM3.

• I can confirm that the SMCLK is active while it is being used by the ADC, please see the attached scope shot I took a few days ago. The device is in LPM3, with a timer interrupt used to trigger a sample and a Sample Complete interrupt used to store the sampled value.

The yellow line shows the ADC sample time – high at start of sample, low when sample complete. The pulse at the end just signifies the end of the sample complete interrupt, where we store the sampled value.

Ignore the blue line – not connected

The pink line is SMCLK – piped out to a pin. You can see that even in LPM3, the SMCLK is running while the ADC sample is being taken.

The green line is MCLK – piped out to a pin. This clearly shows that MCLK is running during the interrupt context, but is switched off during the ADC sample time.

• Tyler Witt said:

I can confirm your calculations, yes 3.2ms would be correct for the sampling time based on the parameters you sent me. Your sampling rate seems pretty slow. Most of the times this speed is around 1MHz, which allows for the oversampling without taking too long.

Is 64 µs about the expected conversion time based on the parameters attached below?

(Attachment removed.  Updated version in later post.)

I reduced the external series resistance until the maximum allowable modulator frequency was well above my source frequency for the modulator.  I've set the modulator frequency to 4 MHz based on my clock setup.  It seems now the conversion time is limited by the clock settings.

Suppose I wanted to minimize the conversion time.  Would the limiting factor be the DCO frequency?  For example, suppose I set the DCO to be 20 MHz, (and therefore f_M = 10 MHz) then I would expect a conversion time of 34.8 µs?

• Jason Work said:
Is 64 µs about the expected conversion time based on the parameters attached below?

Well, the calculation is correct, but I cannot say that 64µs is the correct result, because the maximum allowed modulator clock is 2.3MHz and the calculation uses 4MHz.
So maybe the SD24 doesn't generate any output at all and conversion time is eternal.

Minimum conversion time for OSR=256 within the specs is 111,3µs. = ~9kHz sampling frequency.

• Jason,

Just to reiterate and support what Jens-Michael said, the maximum specified modulator frequency for the SD24_B is 2.3MHz, which when paired with an OSR=256 would give a 111.3us sample time. Even though the numbers in your calculation work out correctly, I wouldn't advise running the modulator at that speed.

The only way to decrease the sample time when already running at the maximum modulator frequency would be to decrease the oversampling rate. However, doing this would affect the accuracy of the SD24_B's output. Section 29.2.7 of the 5xx/6xx User's Guide gives more details on the purpose of the OSR and how it effects the SINC filter and the overall accuracy of the SD_24.

• Tyler said:

...maximum specified modulator frequency for the SD24_B is 2.3MHz

Yes, I now see that.

Reference:
Datasheet MSP430F673x, MSP430F672x Mixed Signal Microcontroller
Find, "Modulator clock frequency"

Why is the maximum modulator frequency some multiple of 32.768 kHz?  Does this assume that ACLK is selected for SD24_B clock source select (SD24SSE)?  Would you help me understand where the dependency on 32.768 KHz is when SMCLK is selected to be the SD24_B clock source?

• Jason Work said:
Why is the maximum modulator frequency some multiple of 32.768 kHz?

It is not. However if you manage to somehow see it - it's just coincidence.

• Ilmars said:

Why is the maximum modulator frequency some multiple of 32.768 kHz?

It is not. However if you manage to somehow see it - it's just coincidence.

[/quote]

I'm basing my comment on this note in the datasheet.

"(1) Modulator clock frequency: MIN = 32.768 kHz - 10% ≈ 30 kHz. MAX = 32.768 kHz × 64 + 10% ≈ 2.3 MHz"

• Jason,

That also puzzled me as I read through it. I think that the limitation should be based off of the Analog Input Characteristics (Section 29.2.6.3 of 5xx/6xx UG).

I also did a few calculations using the formulas in (12) and (13) and none seemed to come out (or be close to) the 2.3MHz level. Also, this explanation still does not explain the multiplicity of the maximum modulator frequency in reference to the 32kHz crystal that is quoted in the datasheet.

I will look into this in more detail and report back to you as I find out more details/insights.

• Tyler Witt said:
Also, this explanation still does not explain the multiplicity of the maximum modulator frequency in reference to the 32kHz crystal that is quoted in the datasheet.

My guess here is that the comment is a hint how to get teh allowed modulation frequency, not an explanation why it is limited.

The 2x family MSPs with SD16 have an internal MODOSC frequency that fits the SD16 clock limit. The SD24_B, especially since it is often mixed with an ADC10_A, does not have a suitable internal clock and must be sourced by MCLK, SMCLK or ACLK (or external clock). So likely, its modulation frequency comes from the DCO, which is usually adjusted by the FLL which uses 32768Hz as reference. The +-10% margin in the datasheet is for the modulation.
So the footnote/comment basically tells, that a DCO adjusted by FLL to REFO*1 to REFO*64 will produce a clock signal for MCLK/SMCLK/ACLK that is within the SD24_B operating range.

But I agree, the way it is written, it is rather confusing than supporting.

• Jens-Michael Gross said:

Is 64 µs about the expected conversion time based on the parameters attached below?

Well, the calculation is correct, but I cannot say that 64µs is the correct result, because the maximum allowed modulator clock is 2.3MHz and the calculation uses 4MHz.

[/quote]

I've now updated my calculation to forbid the SD24_B modulator frequency to exceed the limits imposed by these sources:

• SD24_B, Recommended Operating Conditions, Modulator clock frequency maximum of 2.3 MHz
• Using an FLL-based clock for the SD24_B, the modulator clock frequency must be DCOCLK divided at least by 2.
• f_M maximum based on SD24_B Analog Input Characteristics settling time of the sampling circuit.

Since a SMCLK of 4 Mhz is more desirable than 4.6 MHz, this reduces the f_M below the maximum to 2.0 MHz.  Now my conversion time (with OSR fo 256) is 128 µs.  See attached (removed since there is a more updated version in a later post).

.

• Jason,

As for the explanations behind the datasheet, the calculation based off of the 32kHz crystal assumes the use of the FLL with either an external crystal or the internal REFO. The calculation note is there to explain the odd number itself. These numbers and calculations also don't take into account for the settling time requirements due to the fact that these conditions are heavily reliant on external circuitry.

As always, these datasheet numbers are recommended operation conditions, but are not the absolute ratings for the system. Although we cannot guarantee operation outside these limits, you are welcome to attempt to exceed them to optimize your individual solution.

I hope this answers your questions, let me know if you have more questions.

• All,

Jason asked that I post some results here about the SD24_B conversion time on the MSP430F6736.

My setup was as follows:
DCO via FLL = 8MHz
SMCLK = MCLK = DCO/2 = 4MHz
SD24_B CLK = SMCLK/2 = 2MHz
OSR = 256
Single Channel, single conversion, first conversion creates interrupt
LPM0

When I ran the attached code with the specifications above, I was seeing a sample time close to 138us. This is shown in the picture below. This sampling time was measured by taking the rising edge of P1.0 and measuring the time until MCLK triggered again. The overhead from the calculated value can be attributed to waking from LPM0 partially.

Additionally, I did a test at a modulation frequency greater than 2.3MHz to check if this would work as well. I was able to get good results and saw a sample time of 68.875us with a setup entirely similar to the original setup, but without a predivided SMCLK sourced to the SD24_B. The screenshot for this is shown below.

This seems to indicate that the SD24_B will operate at higher than 2.3MHz for modulation frequency, but again the accuracy and functionality of the SD24_B at this speed can not be guaranteed as it is out of the known spec for this part.

The example code I used to achieve these results is attached here:

4338.SD24_B_SamplingTime.c
//*****************************************************************************
//  Description:
//
//	SD24_B, single conversion on a single channel. Interrupt occurs when a
//	single conversion has completed. Test by applying a voltage to channel 2
//	(SD2P0, SD2N0) and setting a breakpoint at the line indicated below.
//
//	Additionally, sampling time can be performed by connecting a logic analyzer
//  or oscilloscope to both MCLK and P1.0. Trigger on the rising edge of P1.0
//  and the time from the rise of P1.0, to the reactivation of MCLK is roughly
//  the sample time.
//
//  ACLK = 32kHz, MCLK = SMCLK = DCO/2 =  4MHz
//
//  //* For minimum Vcc required for SD24_B module - see datasheet          *//
//  //* 100nF cap between Vref and AVss is recommended when using 1.5V REF  *//
//
//                MSP430F673x
//             -----------------
//         /|\|              XIN|-
//          | |                 | 32kHz Crystal
//          --|RST          XOUT|-
//            |                 |
//            |             PJ.0|--> SMCLK
//    Vin+ -->|SD2P0        PJ.1|--> MCLK
//    Vin- -->|SD2N0        P1.0|--> LED
//            |                 |
//            |            VREF |---+
//            |                 |   |
//            |                 |  -+- 100nF
//            |                 |  -+-
//            |                 |   |
//            |            AVss |---+
//            |                 |
//
//  Built with CCS V5.5
//*****************************************************************************
#include <msp430.h>

/* Unsigned integer to store SD24_B conversion result */
unsigned int results;

int main(void) {
WDTCTL = WDTPW | WDTHOLD;               // Stop WDT

// Setup LED to show conversion time
P1DIR |=  BIT0;						   // LED Output
P1OUT &= ~BIT0;						   // LED Off

// Setup SMCLK output to verify frequency
PJDIR |= BIT0 | BIT1;				   // SMCLK, MCLK output
PJSEL |= BIT0 | BIT1;

// Setup UCS
UCSCTL3 |= SELREF_2;                   // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2;                     // Set ACLK = REFO

__bis_SR_register(SCG0);               // Disable the FLL control loop
UCSCTL0 = 0x0000;                      // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5;                   // Select DCO range 16MHz operation
UCSCTL2 = FLLD_1 | 243;                // Set DCO Multiplier for 8MHz
// (N + 1) * FLLRef = Fdco
// (243 + 1) * 32768 = 8MHz
// Set FLL Div = fDCOCLK/2
UCSCTL4 = SELA_0  | SELS_4  | SELM_4;  // ACLK = XT1, SCLK = MCLK = DCO/2
UCSCTL5 = DIVA__1 | DIVS__2 | DIVM__2; // Set /2 dividers for SCLK and MCLK
__bic_SR_register(SCG0);               // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);

// Loop until XT1, XT2 & DCO fault flag is cleared
do {
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG;                 // Clear fault flags
} while (SFRIFG1 & OFIFG);             // Test oscillator fault flag

SD24BCTL0 = SD24DIV0 | SD24REFS | SD24SSEL_1; // Select internal REF
// Select SMCLK/2 (2MHz) as SD24_B clock source

SD24BCCTL2 |= SD24SNGL | SD24DF_1;     // Single conversion, 2's complement

SD24BINCTL2 |= SD24INTDLY_3;            // Interrupt on 1st sample
SD24BOSR0 = 255;						// OSR = 256
SD24BIE |= SD24IE2;                     // Enable channel 2 interrupt

__delay_cycles(0x3600);                 // Delay for 1.5V REF startup

while (1) {
SD24BCCTL2 |= SD24SC;               // Set bit to start conversion
P1OUT |= BIT0;						// LED On, converting
__bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/ interrupts
__no_operation();
__no_operation();                   // SET BREAKPOINT HERE
}
}

#pragma vector=SD24B_VECTOR
__interrupt void SD24BISR(void) {
switch (SD24BIV) {
case SD24BIV_SD24OVIFG:             // SD24MEM Overflow
break;
case SD24BIV_SD24TRGIFG:            // SD24 Trigger IFG
break;
case SD24BIV_SD24IFG0:              // SD24MEM0 IFG
break;
case SD24BIV_SD24IFG1:              // SD24MEM1 IFG
break;
case SD24BIV_SD24IFG2:              // SD24MEM2 IFG
P1OUT &= ~BIT0;					// Done converting, LED Off
results = SD24BMEMH2;           // Save CH2 results (clears IFG)
break;
}
__bic_SR_register_on_exit(LPM0_bits);   // Exit LPM0
}

.

It is a modified version of a general F6736 code example.

• Tyler Witt said:

... first conversion creates interrupt

How does your result look in this case?  How accurate is it?  How does this compare to the result generated using the default setting of fourth conversion creates interrupt?

• Jason,

All of the results shown above are with the first conversion creating the interrupt. My code example was quickly put together so there is some overhead from the calculated value, but not too much as can be seen in each of the resultant screen shots in my previous post.

If I were to change to the fourth conversion creating the interrupt, it would take roughly 4 times as long as each picture shows.

• I will rephrase my question. Let's change focus from the conversion time to the conversion result. What is your conversion result in volts compared to your expected value?  I am interested in this answer for both first conversion interrupt and fourth conversion interrupt.

• The reason behind the question is that I have changed my single sample reading to interrupt after the first sample and the readings are no longer valid. They are not even slightly close to where they should be, but rather at the very low end.

With the interrupt set to the fourth sample, I get the expected reading of 0mV, but if I interrupt after the first sample, I get readings in the -26000 range.

If I monitor the current consumption, I also notice that it keeps increasing over the duration of the sample period, but only seems to level out near the end. It looks almost as if the sample is delayed while the filter stabalizes, rather than taking a sample and then waiting for the filter to stabalize. The would tie in with the reasoning that if the sample is taken first, (and only 1 sample), then it should make no difference how long it takes the filter to stabalize, as the sample has already been taken. However, this is not the case. Waiting for the filter to stabalize does greatly influence the sample supposedly already taken.

• Allan,

What you are describing is valid and expected behavior of the SD24_B. This module is meant to run continuously, and by using averaging and allowing the filter to settle, the results become much more accurate.

I would like to point your attention to figure 29-8 in the 5xx/5xx UG. The figure there shows the number of conversions as a function of its accuracy to the analog input (% Vfsr). As the graphic shows, it normally takes 4 total conversions to reach maximum accuracy with the SD24_B.

So, while a single conversion will occur in just 128us, these results may not be accurate to the actual input. I would very much suggest that you allow for multiple conversions if your analog input is going to be varying by a wide margin.

• Hi Tyler,

I did see that diagram, but if the ADC is supposed to be running continuously, how is this micro supposed to be a 'Low Power' solution? That ADC and associated voltage reference suck a ton of power. There is no way we could run a low power solution with the SD24B running continuously.

Regards,

Allan

• Allan,

I agree, from a power savings POV, running continuously is not an option.

Instead of this, you can go to LPM, then when you wake up and re-init the VREF, you will need to have 4 conversions in order to ensure that the filter has settled and that the results are correct, then return to LPM. Taking 4 conversions will have to occur every time you wake up (especially if you disable and re-enable the VREF each time), otherwise the results from the SD24_B will not be accurate.

• Hi Tyler,

Another part of the ADC sample process that is not clear to me, is once the sample is complete. The clocks switch off, the reference switches off and the ADC module switches off. The whole process is completed in roughly 500uS.

If I monitor the current, either on the high side, or on the low side, I can see it can take between 10 and 15 mS to return to the expected low levels of LPM3. Can you explain this?

On the attached scope shots, the blue line represents the current as measured by the volt drop across a 1k resistor between the power supply and the target board. Please note how long it takes to return to it's original position.

The yellow and green lines are SMCLK and MCLK respectively and the pink line shows the ADC sample time, from VREF on, 200us delay and then the 4 sample period until the conversion complete interrupt.

High side:

Low Side:

• Hi Tyler,

Back on the 4 samples issues. If we are throwing away the first 3 samples, do we really need to wait the 200uS for the VREF to start up? Three samples at 128uS per sample would be 384uS. This should be more than enough, right?

Allan

• Tyler Witt said:

... you will need to have 4 conversions in order to ensure that the filter has settled and that the results are correct

What will generate a more accurate conversion result?

a) OSR 256, interrupt after first conversion

b) OSR 64, interrupt after fourth conversion

• I was wondering the exact same thing. Does the filter require a fixed time, or 4 conversions?

• Allan/Jason,

I cannot answer your questions off the top of my head. I will dig into this and see what I can find out.

As far as changing the OSR is concerned, I do know that the OSR plays a role in the basic transfer function for the filter as is seen in section 29.2.7.1 and equations (14) and (15).

My initial thought about using the sample time as your reference settling time, is that the filter would not settle until the reference for it had settled, but I can test this out.

I will will post my results here when I get them.

• Allan/Jason,

I have obtained some results for you with the SD24_B. The below Excel file is the summary. Also below is the updated code which I used to get the results.

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/166/4214.f6736_5F00_SD24B_5F00_OSR.xlsx

2450.SD24_B_SamplingTime.c
//*****************************************************************************
//  Description:
//
//	SD24_B, single conversion on a single channel. Interrupt occurs when a
//	single conversion has completed. Test by applying a voltage to channel 2
//	(SD2P0, SD2N0) and setting a breakpoint at the line indicated below.
//
//	Additionally, sampling time can be performed by connecting a logic analyzer
//  or oscilloscope to both MCLK and P1.0. Trigger on the rising edge of P1.0
//  and the time from the rise of P1.0, to the reactivation of MCLK is roughly
//  the sample time.
//
//  ACLK = 32kHz, MCLK = SMCLK = DCO/2 =  4MHz
//
//  //* For minimum Vcc required for SD24_B module - see datasheet          *//
//  //* 100nF cap between Vref and AVss is recommended when using 1.5V REF  *//
//
//                MSP430F673x
//             -----------------
//         /|\|              XIN|-
//          | |                 | 32kHz Crystal
//          --|RST          XOUT|-
//            |                 |
//    Vin+ -->|SD0P0            |
//    Vin- -->|SD0N0        P1.0|--> LED
//            |                 |
//            |            VREF |---+
//            |                 |   |
//            |                 |  -+- 100nF
//            |                 |  -+-
//            |                 |   |
//            |            AVss |---+
//            |                 |
//
//  Built with CCS V5.5
//*****************************************************************************
#include <msp430.h>

/* Unsigned integer to store SD24_B conversion result */
unsigned int results[2];

int main(void) {
WDTCTL = WDTPW | WDTHOLD;               // Stop WDT

// Setup LED to show conversion time
P1DIR |=  BIT0;						   // LED Output
P1OUT &= ~BIT0;						   // LED Off

// Setup UCS
UCSCTL3 |= SELREF_2;                   // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2;                     // Set ACLK = REFO

__bis_SR_register(SCG0);               // Disable the FLL control loop
UCSCTL0 = 0x0000;                      // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5;                   // Select DCO range 16MHz operation
UCSCTL2 = FLLD_1 | 243;                // Set DCO Multiplier for 8MHz
// (N + 1) * FLLRef = Fdco
// (243 + 1) * 32768 = 8MHz
// Set FLL Div = fDCOCLK/2
UCSCTL4 = SELA_0  | SELS_4  | SELM_4;  // ACLK = XT1, SCLK = MCLK = DCO/2
UCSCTL5 = DIVA__1 | DIVS__2 | DIVM__2; // Set /2 dividers for SCLK and MCLK
__bic_SR_register(SCG0);               // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);

// Loop until XT1, XT2 & DCO fault flag is cleared
do {
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG;                 // Clear fault flags
} while (SFRIFG1 & OFIFG);             // Test oscillator fault flag

SD24BCTL0 = SD24DIV0 | SD24REFS | SD24SSEL_1; // Select internal REF
// Select SMCLK/2 (2MHz) as SD24_B clock source

SD24BCCTL0 |= SD24SNGL;     			// Single conversion, offset binary

SD24BINCTL0 |= SD24INTDLY_3;			// Interrupt on 1st sample
//    SD24BINCTL0 |= SD24INTDLY_0;			// Interrupt on 4th sample

SD24BOSR0 = 1023;						// OSR = 1024
//    SD24BOSR0 = 255;						// OSR = 256
//    SD24BOSR0 = 63;							// OSR = 64

SD24BIE |= SD24IE0;           			// Enable channel 0 interrupt

__delay_cycles(0x3600);                 // Delay for 1.5V REF startup

while (1) {
SD24BCCTL0 |= SD24SC;               // Set bit to start conversion
P1OUT |= BIT0;						// LED On, converting
__bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/ interrupts
__no_operation();
}
}

#pragma vector=SD24B_VECTOR
__interrupt void SD24BISR(void) {
static unsigned char index = 0;
switch (SD24BIV) {
case SD24BIV_SD24OVIFG:             // SD24MEM Overflow
break;
case SD24BIV_SD24TRGIFG:            // SD24 Trigger IFG
break;
case SD24BIV_SD24IFG0:              // SD24MEM0 IFG
P1OUT &= ~BIT0;					// Done converting, LED Off
results[index++] = SD24BMEML0;  // Save CH0 results (low 16) (clears IFG)
results[index++] = SD24BMEMH0;  // Save CH0 results (high 16)
if(index >= 2) {    // Both results are done
index = 0;					// SET BREAKPOINT HERE
}
break;
case SD24BIV_SD24IFG1:              // SD24MEM1 IFG
break;
case SD24BIV_SD24IFG2:              // SD24MEM2 IFG
break;
}
__bic_SR_register_on_exit(LPM0_bits);   // Exit LPM0
}

It looks like you would be much better off using an OSR=64 on the 4th sample than any other OSR on the 1st sample. It looks like the results can become very skewed from what you would expect if you attempt to pull the result from the 1st sample (regardless of how many single samples you do).

To explain the Eff OSR column, I was seeing that when the first sample was being used, the full range for the results (as the UG explains in Table 29-3) is not accurate to the output. For example, the highest value I was ever reading with OSR=256 was 0x2B2B00. When the results are scaled to this value (as is done in the Excel sheet), the values are accurate, but this requires knowing what the maximum value would be.

I have not yet tested for the power issue that you were mentioning. How are you triggering your SD24_B conversions? And are you disabling the SD24_B and the REF before you enter LPM? What is your sequence of events for this?

Hopefully the testing I have already done explains the difference between the first sample at OSR=256 and the fourth sample at OSR=64.

• Hi Tyler,

I have disabled the VREF and do not start a conversion. I am running off a timer interrupt with a simply 'while' loop for a small delay and I still see the same 10 to 15 mS decay once the interrupt completes.

I have moved to the TS430PZ100B bare board to rule out any interference from our hardware. I have also disabled the charge pump and turned off the LCD module, but I still can't shake this long decay time.

Are you able to return to an LPM3 current draw quickly? I should be at around 28uA, but it takes as long as 50 to 60mS to return to this level. After 10mS, it is still around 80uA.

Regards,

Allan

• Tyler Witt said:
I agree, from a power savings POV, running continuously is not an option.

Wrong tool for the job, then.
A Delta-Sigma converter isn't meant for taking snapshot samples. It's an ADC design for low-cost, high-precision, low-frequency continuous sampling.

Allan Lester-Olivier said:
Back on the 4 samples issues. If we are throwing away the first 3 samples, do we really need to wait the 200uS for the VREF to start up? Three samples at 128uS per sample would be 384uS. This should be more than enough, right?

No. The SD16 doesn't need these three samples to warm up. Their results (or actually the process of taking them) is part of the conversion process.

To understand why, you need to know how a Delta-Sigma works. This will also answer your other question:

Allan Lester-Olivier said:
I was wondering the exact same thing. Does the filter require a fixed time, or 4 conversions?
Neither-nor. But '4 conversions' is closer to the truth.

Simplified, a Delta-Sigma generates a bitstream. Each clock pulse, one bit is generated. The bits are generated by a combination of a delta stage and an integrator (sigma stage) followed by a comparator. The last generated bit is used as loopback input to the delta stage. So if the integrator output is above reference, a '1' bit is generated and next cycle, the reference is subtracted from the input voltage before integrating.
After an unlimited number of bits, the ratio of '1' bits to the total number of bits is exactly the ratio of input voltage to reference voltage.
Now you cannot wait an unlimited time for the result. Also, there is some redundancy in the output. For, say, 50% Vref, the bitstream would look like 01010101.
So the bitstream is put into a digital filter where it is 'decimated' by some clever algorithm. With an OSR of 256, it takes 1024 bits to give a result. However, a new result is created every 256 bits. Yet the last 768 bits are still required. And exactly the last 768 bits before the current ones. If you stop the conversion, these last bits are stale next time you start the SD16 and the first three conversions are worthless, as they contain 75%, 50% and 25% of stale bits.

This also answers the question about the reference: the reference must have been settled before the first conversion, so that the 4th conversion gives a reliable result.

The SD16 and SD24 ADCs are built to let them run. Without stopping them, without switching channels. Else you have to face the time penalty after each interruption.

• Hi Jean-Michael,

Thanks for a really excellent explanation. It all makes a lot more sense now.

Sadly it takes too much power to leave running, so we will need to still 'snap shot', but at least I now understand why we need to take at least 4 samples and why it is important to have the reference stable for the first sample.

I was looking for 8 samples spaced over a 1 second period, but I could adapt this to take 2 samples 4 times a second, or maybe even 2 samples three times a second.

With this in mind, i.e.averaging multiple samples over a period of 1 second, do we really need a OSR of 256?

We are measuring a fairly slow changing DC signal, but this is for a life safety application, which is why we need multiple samples to ensure we never act on a 'rogue' reading.

Thanks,

Allan

• Allan Lester-Olivier said:
We are measuring a fairly slow changing DC signal, but this is for a life safety application, which is why we need multiple samples to ensure we never act on a 'rogue' reading.

Yes, spikes are always possible and in a life-safety application, it is of course important to avoid any erratic action.

Well, an MSP with ADC10 or ADC12 would have been better for this kind of job (single conversions with long delay between - converisons can even be triggered by timer). Especially since you'll need OSR=1024 to get maximum resolution. (on OSR=32, the SD16 isn't better than the ADC12, just that MSPs with multiple SD16 modules can do simultaneous conversions while the ADC12 can't).

Allan Lester-Olivier said:
With this in mind, i.e.averaging multiple samples over a period of 1 second, do we really need a OSR of 256?

Well, depends. The SD16 is less prone to spike readings than an SAR converter like the ADC12. Actually, a conversion with OSR=256 is built form 1024 comparisons over time. So a short spike will only affect a few bits in the filter and the conversion result won't change much.

What you can do: lower SD16 clock, use OSR=1024, auto-drop the first 3 conversion results and go to sleep once you started the SD16. After 4096 clock ticks (4ms, on 1MHz clock), you'll get a result that is built by 4096 comparisons evenly spread over 4ms. Should be 'average' enough so you won't have to do too many samples per second if your DC signal is really only slowly changing.

• Allan Lester-Olivier said:

8 samples spaced over a 1 second period

5.4 µA average current (calculated) with these inputs:

• SD24INTDLY = 0 (interrupt after fourth conversion)
• OSR =256
• modulator frequency = 2.0 MHz

Allan Lester-Olivier said:

2 samples 4 times a second

4.25 µA average current (calculated.  See attached.)

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/166/5165.MSP430F6736-SD24_5F00_B-conversion-time-and-power.xlsx

Allan Lester-Olivier said:

2 samples three times a second

3.82 µA average current (calculated)