Other Parts Discussed in Thread: TPS3813, TMS320F2808, TPS3813-Q1
Hello,
In my design i am driving nPORRST pin of TMS570lS3137 with active low reset signal from a circuit which is combination of 3137 I/O and Core Voltage Monitor circuit and external watchdog (timer based) circuit. As per the external watchdog circuit once it is powered on generates watchdog fault if it is not strobed periodically from Processor for the configured time duration or period. So during normal operation of the processor the watchdog circuit is periodically driven by strobe signal from Processor, hence no reset is generated. But in during debug mode i.e when we connect emulator and halt the device through break point for a time period more than Watchdog set time, as the strobe is not generated by processor, watchdog circuit generates reset signal to Processor.
So my question is, in debugging mode will processor get resetted due to active low reset at nPORRST due to Watchdog circuit? Or active low signal on nPORRST is ignored once debugging mode is started? Or do we need external means to inhibit reset during debugging mode?
Similarly i have seen the designs based on TMS320F2808 XRS\ reset pin is interfaced with TPS3813-Q1 Processor Supervisory Circuits With Window-Watchdog, where there is no external means of inhibiting the reset from TPS3813 where Processor is in debug mode and not driving the Watchdog strobe. Processor is not getting resetted due to active low signal on XRS pin. Is the same applicable to TSM570LS3137 nPORRST?
With regards
Rajeeva GK