• State Resolved
  • Locked Locked
  • Replies 12 replies
  • Answers 2 answers
  • Subscribers 31 subscribers
  • Views 214 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8353F: IC behavior while being powered OFF/Safe Torque Off State.

Vincent Desjardins
Prodigy 10 points
Part Number: DRV8353F

Tool/software:

In the case where the DRV835X chip is :
  • Used with a dual supply architecture (VM 12V vs Vdrain between 16v-55V)
  • Voltage of Power Mosfets VIN (16V-55V) different from VDRAIN.
When the IC transitions from a normal state of operation to a non energized state ( Scenario of a Safe Torque Off --> Vdrain = 0V and/or VM = 0V) 
  • Would it be harmful on the DRV835X pins GLx if a low power ( inferior to 50 mA) 12V PWM is applied on each of the GLX pins ?
    • If it is, what are the impacts, limitations or alternatives ?
    • If not, is there an expected behavior (Leakage, reverse current flow, etc) of the chip ?
  • 0
    TI__Genius 12231 points

    Hi Vincent, 

    Thank you for posting on our forum! 

    Please allow me to look into your questions and follow-up by the weekend. 

    Best Regards,

    -Joshua

  • 0 in reply to Joshua Maize
    TI__Genius 14345 points

    Hey Joshua,

    Just giving a friendly nudge here, can you please help to provide feedback on the questions above?

    -Matt

  • 0 in reply to Matt Calvo
    TI__Mastermind 22891 points

    Hi Matt, Vincent,

    I apologize for the delay, Joshua is OOO till the end of next week. He will provide an update once he is back. Just for clarification, is the question relating to device behavior if PWMs are continuing to run as the chip is powering down where there could be a case where VDRAIN is less than VM?

    Regards,

    Anthony Lodi

  • 0 in reply to Joshua Maize
    TI__Genius 12231 points

    Hi Vincent, Matt, 

    Thank you for your patience in my leave. 

    As Anthony asked regarding clarification on this inquiry,  I also want to ask if this 12V PWM on GLX is referring to the input pin (INLx) or an external 12V voltage being present on the output GLx pin?

    I think we can better help to more quickly respond after this additional clarification. 

    Best Regards, 

    -Joshua

  • 0 in reply to Joshua Maize
    Prodigy 10 points

    i thanks guys, i think my answer to anthony didnt go through.

    1- the question is when we have no power ( Vm = 0 V and Vdrain = 0V), what will happen if wr drive the low side ) GLx mosfets to use the motor as a passive electrical brake. My concern is the regen voltages could go back in the motor drive chip.

    2 - Regarding the source of the pwm, it would be an external 12V pwm with a max current of 50mA.

    best regards

  • 0 in reply to Vincent Desjardins
    TI__Genius 12231 points

    Hi Vincent,  no worries!

    Thank you for the clarification.  Allow me to look into these instances and follow-up later today with response.  

    Best Regards,

    -Joshua

  • 0 in reply to Joshua Maize
    TI__Genius 12231 points

    Hey Vincent,  

    Vincent Desjardins said:
    1- the question is when we have no power ( Vm = 0 V and Vdrain = 0V), what will happen if wr drive the low side ) GLx mosfets to use the motor as a passive electrical brake. My concern is the regen voltages could go back in the motor drive chip.

    This is an interesting proposition,  but there are a  few considerations:

    • Is this scenario used with dual-supply architecture? (VM and VDRAIN are isolated power supplies from each other or similar setup)
    • How will the lowside FETs be PWMd? Will their gates be connected to an external controller and will this current path be disconnected during normal operation?
    • The only two points that I could see allowing the regenerative voltage to enter back into the device is through the VDRAIN pin which is used for VDRAIN voltage sensing/ reference for the charge pump, and the CSA sensing inputs that are connected through a low resistance rsense resistor to GND.
    • However,  it's likely the VDRAIN sensing circuit will be closed when the device is not powered and thus the main direction of regen-current will be flowing back into the battery through the highside FET body diode.
    • Lastly,  is there a reason this method of regenerative passive-braking is considered instead of the typical regulae and passive braking methods used when the device is powered (lowside/highside braking,  Hi-Z, etc)? It might be more simple if possible to use other methods. 

    I hope this information is helpful and I look forward to your response!

    Best Regards, 

    -Joshua

  • 0 in reply to Joshua Maize
    Prodigy 10 points

    Hi Joshua,

    • YEs we use a dual power-supply architecture. 
    Vincent Desjardins said:
    In the case where the DRV835X chip is :
    • Used with a dual supply architecture (VM 12V vs Vdrain between 16v-55V)
    • Voltage of Power Mosfets VIN (16V-55V) different from VDRAIN.
    • Yes
      Joshua Maize said:
      Will their gates be connected to an external controller and will this current path be disconnected during normal operation?
    • With our constraint and Safety requirements, is simpler to have passive electrical brake.

    Best regards,

  • 0 in reply to Vincent Desjardins
    TI__Genius 12231 points

    Thank you for the clarifications, Vincent. 

    Lastly, are the GLX inputs going to be connected to both the driver and the FETs when the driver is off? There are internal pull-downs inside the driver that may disrupt the ability to turn on the FETs if not isolated from the driver. 

    This is the next big consideration for a design like this. 

    Best Regards, 

    -Joshua

  • 0 in reply to Joshua Maize
    Prodigy 10 points

    HI, Yes you are correct. The GLx pins will be connected to the MOSFET Gate & the External driver. See image below for the external Driver circuitry. 

  • 0 in reply to Vincent Desjardins
    TI__Genius 12231 points

    Hi Vincent,  

    Thank you for the confirmation and diagram. 

    Please expect another response on the matter within a day after further review.

    Best Regards,

    -Joshua

  • +1 in reply to Joshua Maize
    TI__Genius 12231 points

    Hi Vincent, 

    After review I do not believe the regenerative voltages should cause much issue in the driver itself as that current path returning through the FET body diodes should be tolerable. However, I am still not confident that there will be no abnormalities when driving the FETs externally while still connected to the driver. It may be possible the low current and voltage conduct through the internal pre-driver high-side body diode into VGLS, or be pulled-down due to the passives internally. Despite this, I do not expect any damage to occur, but may still caution to the possible effects of this configuration. 

    Please reach out further if you have any additional questions!

    Best Regards,

    -Joshua