Tool/software:
Hi expert,
Could DRV8860 DOUT pin left floated? We are trying to use 2 chips DRV8860 (U1 DOUT connect to U2 DIN) but no need for fault reading so left U2 DOUT floated. Is there any problems?
And we found when powered on, all channels are on (internal MOSs are turned on), why's that?
Thanks!
Joyce
Hello Joyce,
Could DRV8860 DOUT pin left floated? We are trying to use 2 chips DRV8860 (U1 DOUT connect to U2 DIN) but no need for fault reading so left U2 DOUT floated. Is there any problems?
Yes if you don't care about the Fault-Reg contents or don't need Read Control Register command and Read Data Register command, DOUT can be left floating.
And we found when powered on, all channels are on (internal MOSs are turned on), why's that?
To clarify the 2nd question: after powered on with no load, all OUTx are low as 0V. Is it because we have a current sink at OUTx side?
Did the OUTx have loads connected to VM and no clock applied to CLK and no Latch input? What was the ENABLE state? At power on reset after VM is applied all the output D-FF are cleared which means FETs will not be conducting.
And the 3rd question: When we try 600kHz CLK, the output cannot be controlled. And if we lower the frequency to 100kHz, it works. Which spec should we refer to to select the data rate (CLK frequency)? Is the digital filter affecting this?
See MIN tCLK specification in the datasheet - below screen capture. So the maximum CLK frequency is 1/5 us = 200 kHz with symmetrical high and low times. So below 200 kHz should work. 600 kHz is not supported.
Regards, Murugavel
Hi Murugavel,
Yes if you don't care about the Fault-Reg contents or don't need Read Control Register command and Read Data Register command, DOUT can be left floating.
Understood and solved.
Did the OUTx have loads connected to VM and no clock applied to CLK and no Latch input? What was the ENABLE state? At power on reset after VM is applied all the output D-FF are cleared which means FETs will not be conducting.
No loads connected, no CLK, no LATCH, ENABLE keep high. Is it because this 30uA current sink that will put OUTx low when no load?
See MIN tCLK specification in the datasheet - below screen capture. So the maximum CLK frequency is 1/5 us = 200 kHz with symmetrical high and low times. So below 200 kHz should work. 600 kHz is not supported.
Why didn't I find this part in my datasheet? Oh, I downloaded the Chinese version and it's not the latest! Without the part you showed as your screenshot! I think ti.com need to refresh the Chinese version... Understood and solved!
Thanks!
Joyce
