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DRV10866: FG Jitter and using it to phase lock

Part Number: DRV10866

Hello E2E,

I have a question in regards to using the FG pin on the DRV10866.

Is the FG signal derived directly from BEMF detection (some analog comparator output) or is it gets synced to an internal clock?  

 The reason for the question is we would like to phase lock the motor to another system within 1us of phase jitter - is the FG signal usable in the feedback loop as a reliable proxy for motor position?  

If it gets 'reclocked' which results in the FG signal being quantized by the internal clock, it will mess up the intended VCO control loops which are attempting to phase lock the two systems.

I realize this is a low cost fan driver part not probably not intended for this purpose and that there are drivers with 'true' back-emf signals - but would like to know if this is the case for the DRV10866 part. If this isn't possible with the DRV10866, can you recommend a similar part with this feature?

I did find this post, but it still left some questions unanswered.

Thank you!